公开(公告)号：US20140175539A1

公开(公告)日：2014-06-26

申请号：US14192158

申请日：2014-02-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Thilo Scheiper

IPC: H01L29/78

CPC classification number: H01L29/7827 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/66666 ,  H01L29/78 ,  H01L29/7848

Abstract: Lithographic limitations on gate and induced channel length in MOSFETS are avoided by forming non-planar MOSFETS in a cavity extending into a semiconductor substrate. The gate insulator and channel region lie proximate a cavity sidewall having angle α preferably about ≧90 degrees with respect to the semiconductor surface. The channel length depends on the bottom depth of the cavity and the depth from the surface of a source or drain region adjacent the cavity. The corresponding drain or source lies at the cavity bottom. The cavity sidewall extends therebetween. Neither depth is lithographic dependent. Very short channels can be consistently formed, providing improved performance and manufacturing yield. Source, drain and gate connections are brought to the same surface so that complex circuits can be readily constructed. The source and drain regions are preferably formed epitaxially and strain inducing materials can be used therein to improve channel carrier mobility.

Abstract translation: 通过在延伸到半导体衬底的腔中形成非平面MOSFET，可以避免MOSFETS中栅极和感应沟道长度的光刻限制。 栅极绝缘体和沟道区域靠近具有相对于半导体表面的角度α优选地约≥90度的空腔侧壁。 通道长度取决于空腔的底部深度以及与空腔相邻的源极或漏极区域的表面的深度。 相应的漏极或源极位于腔底。 空腔侧壁在其间延伸。 两个深度都不依赖于光刻。 可以一贯形成非常短的通道，从而提高性能和制造成品率。 源极，漏极和栅极连接被带到相同的表面，使得可以容易地构造复杂的电路。 源区和漏区优选地外延形成，并且应变诱导材料可用于其中以改善沟道载流子迁移率。

公开(公告)号：US20140027825A1

公开(公告)日：2014-01-30

申请号：US14039450

申请日：2013-09-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tim Baldauf ,  Andy Wei ,  Tom Herrmann ,  Stefan Flachowsky ,  Ralf Illgen

IPC: H01L29/78

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L27/0886

Abstract: When forming sophisticated multiple gate transistors and planar transistors in a common manufacturing sequence, the threshold voltage characteristics of the multiple gate transistors may be intentionally “degraded” by selectively incorporating a dopant species into corner areas of the semiconductor fins, thereby obtaining a superior adaptation of the threshold voltage characteristics of multiple gate transistors and planar transistors. In advantageous embodiments, the incorporation of the dopant species may be accomplished by using the hard mask, which is also used for patterning the self-aligned semiconductor fins.

Abstract translation: 当在共同的制造顺序中形成复杂的多栅极晶体管和平面晶体管时，通过选择性地将掺杂剂物质结合到半导体鳍片的角区域中，可以有意地“降低”多个栅极晶体管的阈值电压特性，从而获得 多个栅极晶体管和平面晶体管的阈值电压特性。 在有利的实施方案中，可以通过使用硬掩模来实现掺杂物种的掺入，该硬掩模也用于图案化自对准半导体鳍片。

公开(公告)号：US09966466B2

公开(公告)日：2018-05-08

申请号：US15231105

申请日：2016-08-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Ralf Illgen

IPC: H01L21/02 ,  H01L29/78 ,  H01L21/28 ,  H01L21/762 ,  H01L21/324 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/7849 ,  H01L21/02181 ,  H01L21/02356 ,  H01L21/28291 ,  H01L21/324 ,  H01L21/76251 ,  H01L21/76254 ,  H01L29/66742 ,  H01L29/786 ,  H01L29/78654

Abstract: A semiconductor-on-insulator wafer includes a support substrate, an electrically insulating layer over the support substrate and a semiconductor layer over the electrically insulating layer. A semiconductor structure includes a transistor. The transistor includes an electrically insulating layer including a piezoelectric material over a support substrate, a semiconductor layer over the electrically insulating layer, a source region, a channel region and a drain region in the semiconductor layer, a gate structure over the channel region, a first electrode and a second electrode. The first electrode and the second electrode are provided at laterally opposite sides of the electrically insulating layer. The first and second electrodes are electrically insulated from the semiconductor layer and configured for applying a voltage to the piezoelectric material of the electrically insulating layer. The piezoelectric material creates a strain at least in the channel region in response to the voltage applied thereto.

公开(公告)号：US20170338350A1

公开(公告)日：2017-11-23

申请号：US15234361

申请日：2016-08-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Ralf Illgen

IPC: H01L29/78 ,  H01L29/51 ,  H01L21/02 ,  H01L21/266 ,  H01L29/08 ,  H01L21/3115 ,  H01L21/28 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/78391 ,  H01L21/02181 ,  H01L21/02321 ,  H01L21/266 ,  H01L21/28185 ,  H01L21/31155 ,  H01L29/0847 ,  H01L29/40111 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/512 ,  H01L29/516 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6684

Abstract: The present disclosure provides a semiconductor device including a substrate, a gate structure formed over the substrate, the gate structure including a first ferroelectric material having a first remanent polarization and a second ferroelectric material having a second remanent polarization, the first remanent polarization being smaller than the second remanent polarization, and source and drain regions formed in the substrate, the source and drain regions being laterally separated by a channel region extending along a length direction below the gate structure, wherein the first ferroelectric material and the second ferroelectric material are stacked in a plane parallel to an upper surface of the substrate.

公开(公告)号：US20170200743A1

公开(公告)日：2017-07-13

申请号：US15467305

申请日：2017-03-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Ralf Illgen

IPC: H01L27/12 ,  H01L21/308 ,  H01L21/3105 ,  H01L29/78 ,  H01L21/324 ,  H01L21/84 ,  H01L29/06 ,  H01L29/66 ,  H01L21/265 ,  H01L21/3213

CPC classification number: H01L27/1207 ,  H01L21/26513 ,  H01L21/308 ,  H01L21/31051 ,  H01L21/32139 ,  H01L21/324 ,  H01L21/84 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7833

Abstract: A semiconductor structure includes a semiconductor substrate, a layer of electrically insulating material above the semiconductor substrate, and a layer of semiconductor material above the layer of electrically insulating material. A first transistor includes a first source region, a first drain region, and a first channel region formed in the semiconductor substrate, a first gate insulation layer positioned above the first channel region, and an electrically conductive first gate electrode, wherein the first gate insulation layer includes a first portion of the electrically insulating material. A second transistor includes a second source region, a second drain region, and a second channel region formed in the layer of semiconductor material, a second gate insulation layer positioned above the second channel region, and an electrically conductive second gate electrode, wherein a second portion of the layer of electrically insulating material is positioned below the second channel region.

公开(公告)号：US20160315162A1

公开(公告)日：2016-10-27

申请号：US15201838

申请日：2016-07-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Peter Javorka ,  Jan Hoentschel ,  Stefan Flachowsky

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/51 ,  H01L29/49

CPC classification number: H01L29/42376 ,  H01L21/28008 ,  H01L21/28052 ,  H01L21/28114 ,  H01L21/28123 ,  H01L29/4933 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66575 ,  H01L29/78

Abstract: A semiconductor device structure includes an active region positioned in a semiconductor substrate and a gate structure of a transistor positioned above the active region. The gate structure includes a gate insulating layer, a gate metal layer positioned above the gate insulating layer and a trimmed gate electrode material layer positioned above the gate metal layer. A length of at least a portion of the trimmed gate electrode material layer in a gate length direction of the transistor is less than a length of at least the gate metal layer in the gate length direction.

Abstract translation: 半导体器件结构包括位于半导体衬底中的有源区和位于有源区上方的晶体管的栅极结构。 栅极结构包括栅极绝缘层，位于栅极绝缘层上方的栅极金属层和位于栅极金属层上方的修整的栅电极材料层。 在晶体管的栅极长度方向上的修整的栅电极材料层的至少一部分的长度小于栅极金属层在栅极长度方向上的长度。

公开(公告)号：US09449972B1

公开(公告)日：2016-09-20

申请号：US14640151

申请日：2015-03-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Ralf Illgen ,  Jan Hoentschel

IPC: H01L29/51 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/28 ,  H01L27/088 ,  H01L29/423 ,  H01L27/11 ,  H01L21/311 ,  H01L21/3065

CPC classification number: H01L27/0886 ,  H01L21/28291 ,  H01L21/823431 ,  H01L21/823462 ,  H01L29/42364 ,  H01L29/512 ,  H01L29/516 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66553 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/7851

Abstract: The present disclosure provides, in a first aspect, a semiconductor device, including a semiconductor substrate and a gate structure formed over the semiconductor substrate, wherein the gate structure comprises a fin and a ferroelectric high-k material formed at least over sidewall surfaces of the fin. Herein, a first thickness defined by a thickness of the ferroelectric high-k material formed over sidewalls of the fin is substantially greater than a second thickness defined by a thickness of the ferroelectric high-k material formed over an upper surface of the fin.

Abstract translation: 本公开在第一方面提供一种半导体器件，其包括形成在半导体衬底上的半导体衬底和栅极结构，其中栅极结构包括鳍状物和至少形成在所述半导体衬底的侧壁表面上的铁电高k材料 鳍。 这里，由在翅片的侧壁上形成的铁电高k材料的厚度限定的第一厚度基本上大于由在翅片的上表面上形成的铁电高k材料的厚度限定的第二厚度。

公开(公告)号：US20160268271A1

公开(公告)日：2016-09-15

申请号：US15162151

申请日：2016-05-23

Applicant: GLOBALFOUNDRIES Inc. ,  Fraunhofer Gesellschaft zur Foerderung der angewandten Forschung e.V. ,  NaMLab gGmbH

Inventor： Johannes Mueller ,  Stefan Mueller ,  Stefan Flachowsky

IPC: H01L27/115 ,  H01L21/28 ,  H01L29/78

CPC classification number: H01L27/11507 ,  H01L21/28291 ,  H01L29/513 ,  H01L29/516 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6684 ,  H01L29/78391

Abstract: A method disclosed herein includes providing a semiconductor structure, the semiconductor structure comprising a semiconductor substrate and a gate stack, the gate stack comprising a gate insulation material over the substrate, a floating gate electrode material over the gate insulation material, a ferroelectric transistor dielectric over the floating gate electrode material and a top electrode material over the ferroelectric transistor dielectric, performing a first patterning process to remove portions of the top electrode material and the ferroelectric transistor dielectric and performing a second patterning process after the first patterning process to remove portions of the floating gate electrode material and the gate insulation material, wherein a projected area of an upper portion of the gate structure onto a plane that is perpendicular to a thickness direction of the substrate is smaller than a projected area of the lower portion of the gate structure onto the plane.

Abstract translation: 本文公开的方法包括提供半导体结构，所述半导体结构包括半导体衬底和栅极堆叠，所述栅极堆叠在衬底上包括栅极绝缘材料，栅极绝缘材料上方的浮置栅电极材料，铁电晶体管绝缘体 所述浮栅电极材料和所述铁电晶体管电介质上的顶电极材料，执行第一图案化工艺以去除所述顶电极材料和所述铁电晶体管电介质的部分，并且在所述第一图案化工艺之后执行第二图案化工艺以去除所述 浮栅电极材料和栅极绝缘材料，其中栅极结构的上部的投影面积垂直于衬底的厚度方向的平面上的尺寸小于栅极结构的下部的投影面积， 飞机。

公开(公告)号：US20160260714A1

公开(公告)日：2016-09-08

申请号：US14640151

申请日：2015-03-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Stefan Flachowsky ,  Ralf Illgen ,  Jan Hoentschel

IPC: H01L27/088 ,  H01L21/311 ,  H01L29/423 ,  H01L27/11 ,  H01L21/8234 ,  H01L29/51

CPC classification number: H01L27/0886 ,  H01L21/28291 ,  H01L21/823431 ,  H01L21/823462 ,  H01L29/42364 ,  H01L29/512 ,  H01L29/516 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66553 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/7851

Abstract: The present disclosure provides, in a first aspect, a semiconductor device, including a semiconductor substrate and a gate structure formed over the semiconductor substrate, wherein the gate structure comprises a fin and a ferroelectric high-k material formed at least over sidewall surfaces of the fin. Herein, a first thickness defined by a thickness of the ferroelectric high-k material formed over sidewalls of the fin is substantially greater than a second thickness defined by a thickness of the ferroelectric high-k material formed over an upper surface of the fin.

Abstract translation: 本公开在第一方面提供一种半导体器件，其包括形成在半导体衬底上的半导体衬底和栅极结构，其中栅极结构包括鳍状物和至少形成在所述半导体衬底的侧壁表面上的铁电高k材料 鳍。 这里，由在翅片的侧壁上形成的铁电高k材料的厚度限定的第一厚度基本上大于由在翅片的上表面上形成的铁电高k材料的厚度限定的第二厚度。

公开(公告)号：US20160233318A1

公开(公告)日：2016-08-11

申请号：US14615529

申请日：2015-02-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Peter Javorka ,  Jan Hoentschel ,  Stefan Flachowsky

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/42392 ,  H01L29/66772 ,  H01L29/78696

Abstract: The present disclosure provides a method of forming a semiconductor device and a semiconductor device. An SOI substrate portion having a semiconductor layer, a buried insulating material layer and a bulk substrate is provided, wherein the buried insulating material layer is interposed between the semiconductor layer and the bulk substrate. The SOI substrate portion is subsequently patterned so as to form a patterned bi-layer stack on the bulk substrate, which bi-layer stack comprises a patterned semiconductor layer and a patterned buried insulating material layer. The bi-layer stack is further enclosed with a further insulating material layer and an electrode material is formed on and around the further insulating material layer. Herein a gate electrode is formed by the bulk substrate and the electrode material such that the gate electrode substantially surrounds a channel portion formed by a portion of the patterned buried insulating material layer.

Abstract translation: 本公开提供了形成半导体器件和半导体器件的方法。 提供具有半导体层，掩埋绝缘材料层和体基板的SOI衬底部分，其中埋入绝缘材料层插入在半导体层和块状衬底之间。 SOI衬底部分随后被图案化以便在本体衬底上形成图案化的双层堆叠，该双层堆叠包括图案化的半导体层和图案化的掩埋绝缘材料层。 双层堆叠进一步被另外的绝缘材料层封闭，并且在另外的绝缘材料层上和周围形成电极材料。 这里，栅电极由体基板和电极材料形成，使得栅电极基本上围绕由图案化的掩埋绝缘材料层的一部分形成的沟道部分。