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    METHODS OF FORMING FINS FOR A FINFET DEVICE BY FORMING AND REPLACING SACRIFICIAL FIN STRUCTURES WITH ALTERNATIVE MATERIALS
    91.
    发明申请
    METHODS OF FORMING FINS FOR A FINFET DEVICE BY FORMING AND REPLACING SACRIFICIAL FIN STRUCTURES WITH ALTERNATIVE MATERIALS 有权
    通过形成和替换具有替代材料的精密结构的FINFET器件形成FIS的方法

    公开(公告)号：US20160027895A1

    公开(公告)日：2016-01-28

    申请号：US14341000

    申请日：2014-07-25

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Murat Kerem Akarvardar ,  Ajey Poovannummoottil Jacob

    IPC: H01L29/66 ,  H01L21/02

    CPC classification number: H01L29/1054 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7854

    Abstract: One illustrative method disclosed herein includes, among other things, forming a sacrificial fin structure above a semiconductor substrate, forming a layer of insulating material around the sacrificial fin structure, removing the sacrificial fin structure so as to define a replacement fin cavity in the layer of insulating material that exposes an upper surface of the substrate, forming a replacement fin in the replacement fin cavity on the exposed upper surface of the substrate, recessing the layer of insulating material, and forming a gate structure around at least a portion of the replacement fin exposed above the recessed layer of insulating material.

    Abstract translation: 本文公开的一种说明性方法包括在半导体衬底之上形成牺牲鳍结构，在牺牲鳍结构周围形成绝缘材料层，去除牺牲鳍结构，以便在 绝缘材料，其暴露衬底的上表面，在所述衬底的暴露的上表面上的替换翅片腔中形成替换翅片，使所述绝缘材料层凹陷，以及在所述替换鳍片的至少一部分周围形成栅极结构 暴露在绝缘材料的凹陷层上方。

    TRANSISTORS COMPRISING DOPED REGION-GAP-DOPED REGION STRUCTURES AND METHODS OF FABRICATION
    92.
    发明申请
    TRANSISTORS COMPRISING DOPED REGION-GAP-DOPED REGION STRUCTURES AND METHODS OF FABRICATION 有权
    包含区域划分区域结构的晶体管和制造方法

    公开(公告)号：US20160020335A1

    公开(公告)日：2016-01-21

    申请号：US14334950

    申请日：2014-07-18

    Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

    Inventor： Steven J. Bentley ,  Ajey Poovannummoottil Jacob ,  Chia-Yu Chen ,  Tenko Yamashita

    IPC: H01L29/808 ,  H01L29/45 ,  H01L29/66

    CPC classification number: H01L29/495 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/02532 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/167 ,  H01L29/42376 ,  H01L29/45 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/78

    Abstract: Embodiments of the present invention provide transistors with controlled junctions and methods of fabrication. A dummy spacer is used during the majority of front end of line (FEOL) processing. Towards the end of the FEOL processing, the dummy spacers are removed and replaced with a final spacer material. Embodiments of the present invention allow the use of a very low-k material, which is highly thermally-sensitive, by depositing it late in the flow. Additionally, the position of the gate with respect to the doped regions is highly controllable, while dopant diffusion is minimized through reduced thermal budgets. This allows the creation of extremely abrupt junctions whose surface position is defined using a sacrificial spacer. This spacer is then removed prior to final gate deposition, allowing a fixed gate overlap that is defined by the spacer thickness and any diffusion of the dopant species.

    Abstract translation: 本发明的实施例提供具有受控结的晶体管和制造方法。 在大多数前端（FEOL）处理中使用虚拟间隔器。 在FEOL处理结束之后，去除虚拟间隔物并用最后的间隔物材料代替。 本发明的实施例允许使用非常低k的材料，其通过在流动中较晚沉积而具有高度热敏感性。 此外，栅极相对于掺杂区域的位置是高度可控的，而掺杂剂扩散通过减少的热预算被最小化。 这允许创建极其突出的接头，其表面位置使用牺牲隔离物限定。 然后在最终栅极沉积之前去除该间隔物，允许由间隔物厚度和掺杂剂物质的任何扩散限定的固定栅极重叠。

    METHODS OF FORMING SUBSTANTIALLY DEFECT-FREE, FULLY-STRAINED SILICON-GERMANIUM FINS FOR A FINFET SEMICONDUCTOR DEVICE
    96.
    发明申请
    METHODS OF FORMING SUBSTANTIALLY DEFECT-FREE, FULLY-STRAINED SILICON-GERMANIUM FINS FOR A FINFET SEMICONDUCTOR DEVICE 有权
    形成用于FINFET半导体器件的基本无缺陷，全应变硅 - 锗元件的方法

    公开(公告)号：US20150279973A1

    公开(公告)日：2015-10-01

    申请号：US14242472

    申请日：2014-04-01

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Murat Kerem Akarvardar ,  Jody A. Fronheiser ,  Ajey Poovannummoottil Jacob

    IPC: H01L29/66 ,  H01L29/10 ,  H01L21/84

    CPC classification number: H01L29/66795 ,  H01L29/1054

    Abstract: One illustrative method disclosed herein includes, among other things, performing an epitaxial deposition process to form an epi SiGe layer above a recessed layer of insulating material and on an exposed portion of a fin, wherein the concentration of germanium in the layer of epi silicon-germanium (SixGe1-x) is equal to or greater than a target concentration of germanium for the final fin, performing a thermal anneal process in an inert processing environment to cause germanium in the epi SiGe to diffuse into the fin and thereby define an SiGe region in the fin, after performing the thermal anneal process, performing at least one process operation to remove the epi SiGe and, after removing the epi SiGe, forming a gate structure around at least a portion of the SiGe region.

    Abstract translation: 本文公开的一种说明性方法包括进行外延沉积工艺以在绝缘材料的凹陷层上方和鳍的暴露部分上形成外延SiGe层，其中外延硅 - 锗（SixGe1-x）等于或大于用于最终翅片的锗的目标浓度，在惰性处理环境中进行热退火工艺以使外延SiGe中的锗扩散到翅片中，从而限定SiGe区域 在翅片中，在进行热退火处理之后，进行至少一个处理操作以去除外延SiGe，并且在去除外延SiGe之后，在SiGe区域的至少一部分周围形成栅极结构。

    METHODS OF FORMING A NON-PLANAR ULTRA-THIN BODY DEVICE
    97.
    发明申请
    METHODS OF FORMING A NON-PLANAR ULTRA-THIN BODY DEVICE 审中-公开
    形成非平面超薄体器件的方法

    公开(公告)号：US20150255555A1

    公开(公告)日：2015-09-10

    申请号：US14197686

    申请日：2014-03-05

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Ruilong Xie ,  Ajey Poovannummoottil Jacob ,  Michael Hargrove ,  William J. Taylor, Jr.

    IPC: H01L29/423 ,  H01L29/66 ,  H01L29/78

    CPC classification number: H01L29/66795 ,  H01L29/1054 ,  H01L29/785

    Abstract: One illustrative method disclosed herein involves, among other things, forming a first epi semiconductor material on the exposed opposite sidewalls of a fin to thereby define a semiconductor body, performing at least one etching process to remove at least a portion of the substrate portion of the fin positioned between the first epi semiconductor materials positioned on the opposite sidewalls of the fin and to thereby define a back-gate cavity, forming a back-gate insulating material within the back-gate cavity and on the first epi semiconductor materials, forming a back-gate electrode on the back-gate insulation material within the back-gate cavity and forming a gate structure comprised of a gate insulation layer and a gate electrode around the semiconductor bodies.

    Abstract translation: 本文公开的一种说明性方法除其他外包括在鳍的暴露的相对侧壁上形成第一外延半导体材料，从而限定半导体本体，执行至少一个蚀刻工艺以去除衬底部分的至少一部分 翅片定位在位于翅片的相对侧壁上的第一外延半导体材料之间，从而限定背栅腔，在背栅腔内和第一外延半导体材料上形成背栅绝缘材料，形成背 在后栅极腔内的背栅极绝缘材料上形成栅极电极，并且形成由半导体本体周围的栅极绝缘层和栅极电极构成的栅极结构。

    METHODS OF FORMING A NON-PLANAR ULTRA-THIN BODY SEMICONDUCTOR DEVICE AND THE RESULTING DEVICES
    98.
    发明申请
    METHODS OF FORMING A NON-PLANAR ULTRA-THIN BODY SEMICONDUCTOR DEVICE AND THE RESULTING DEVICES 有权
    形成非平面超薄体半导体器件和结果器件的方法

    公开(公告)号：US20150228792A1

    公开(公告)日：2015-08-13

    申请号：US14175113

    申请日：2014-02-07

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ajey Poovannummoottil Jacob ,  Ruilong Xie ,  Michael Hargrove

    IPC: H01L29/78 ,  H01L21/306 ,  H01L29/51 ,  H01L21/02 ,  H01L29/16 ,  H01L29/66

    CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/51 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/778

    Abstract: One device disclosed includes a gate structure positioned around a perimeter surface of the fin, a layer of channel semiconductor material having an axial length in the channel length direction of the device that corresponds approximately to the overall width of the gate structure being positioned between the gate structure and around the outer perimeter surface of the fin, wherein an inner surface of the layer of channel semiconductor material is spaced apart from and does not contact the outer perimeter surface of the fin. One method disclosed involves, among other things, forming first and second layers of semiconductor material around the fin, forming a gate structure around the second semiconductor material, removing the portions of the first and second layers of semiconductor material positioned laterally outside of sidewall spacers and removing the first layer of semiconductor material positioned below the second layer of semiconductor material.

    Abstract translation: 所公开的一种装置包括围绕翅片的周边表面定位的栅极结构，沟道半导体材料层，其在器件的沟道长度方向上具有轴向长度，其大致对应于位于栅极之间的栅极结构的总宽度 结构并且围绕翅片的外周表面周围，其中沟道半导体材料层的内表面与翅片的外周表面间隔开并且不接触鳍的外周表面。 公开的一种方法尤其涉及在翅片周围形成第一和第二层半导体材料，围绕第二半导体材料形成栅极结构，去除位于侧壁间隔横向外侧的第一和第二半导体层的部分，以及 去除位于第二半导体材料层下方的第一半导体材料层。

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