公开(公告)号：US10340273B2

公开(公告)日：2019-07-02

申请号：US15409435

申请日：2017-01-18

Applicant: Intel Corporation

Inventor： Chia-Hong Jan ,  Walid M Hafez ,  Jeng-Ya David Yeh ,  Hsu-Yu Chang ,  Neville L Dias ,  Chanaka D Munasinghe

IPC: H01L27/092 ,  H01L21/82 ,  H01L29/10 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L21/225 ,  H01L29/06 ,  H01L29/08

Abstract: An impurity source film is formed along a portion of a non-planar semiconductor fin structure. The impurity source film may serve as source of an impurity that becomes electrically active subsequent to diffusing from the source film into the semiconductor fin. In one embodiment, an impurity source film is disposed adjacent to a sidewall surface of a portion of a sub-fin region disposed between an active region of the fin and the substrate and is more proximate to the substrate than to the active area.

公开(公告)号：US10340220B2

公开(公告)日：2019-07-02

申请号：US15748608

申请日：2015-08-26

Applicant: Intel Corporation

Inventor： Chen-Guan Lee ,  Vadym Kapinus ,  Pei-Chi Liu ,  Joodong Park ,  Walid M. Hafez ,  Chia-Hong Jan

IPC: H01L23/522 ,  H01L27/06 ,  H01L49/02 ,  H01L29/78 ,  H01L21/86 ,  H01L29/786

Abstract: IC device structures including a lateral compound resistor disposed over a surface of a substrate, and fabrication techniques to form such a resistor in conjunction with fabrication of a transistor. Rather than being stacked vertically, a compound resistive trace may include a plurality of resistive materials arranged laterally over a substrate. Along a resistive trace length, a first resistive material is in contact with a sidewall of a second resistive material. A portion of a first resistive material along a centerline of the resistive trace may be replaced with a second resistive material so that the second resistive material is embedded within the first resistive material.

公开(公告)号：US20190051806A1

公开(公告)日：2019-02-14

申请号：US16074151

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Kinyip Phoa ,  Jui-Yen Lin ,  Nidhi Nidhi ,  Chia-Hong Jan

IPC: H01L35/28 ,  H01L35/14 ,  H01L35/04 ,  H01L29/78

Abstract: An apparatus includes a first semiconductor fin and a second semiconductor fin that is parallel to the first semiconductor fin. The first semiconductor fin extends from a first region of a substrate near a circuit that produces thermal energy when a circuit is in operation to a second region of the substrate, which is disposed away from the circuit. The second semiconductor fin extends from the first region to the second region and has a different material composition than the first semiconductor fin. The first and second semiconductor fins collectively exhibit a Seebeck effect when the circuit is in operation. The apparatus includes interconnects to couple the first and second semiconductor fins to a power supply circuit to transfer electricity generated due to the Seebeck effect to the power supply circuit.

公开(公告)号：US10115721B2

公开(公告)日：2018-10-30

申请号：US15167006

申请日：2016-05-27

Applicant: INTEL CORPORATION

Inventor： Walid M. Hafez ,  Peter J Vandervoorn ,  Chia-Hong Jan

IPC: H01L29/76 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/16 ,  H01L29/161

Abstract: Techniques are disclosed for forming a planar-like transistor device on a fin-based field-effect transistor (finFET) architecture during a finFET fabrication process flow. In some embodiments, the planar-like transistor can include, for example, a semiconductor layer which is grown to locally merge/bridge a plurality of adjacent fins of the finFET architecture and subsequently planarized to provide a high-quality planar surface on which the planar-like transistor can be formed. In some instances, the semiconductor merging layer can be a bridged-epi growth, for example, comprising epitaxial silicon. In some embodiments, such a planar-like device may assist, for example, with analog, high-voltage, wide-Z transistor fabrication. Also, provision of such a planar-like device during a finFET flow may allow for the formation of transistor devices, for example, exhibiting lower capacitance, wider Z, and/or fewer high electric field locations for improved high-voltage reliability, which may make such devices favorable for analog design, in some instances.

公开(公告)号：US09972642B2

公开(公告)日：2018-05-15

申请号：US15784318

申请日：2017-10-16

Applicant: Intel Corporation

Inventor： Walid M. Hafez ,  Jeng-Ya D. Yeh ,  Curtis Tsai ,  Joodong Park ,  Chia-Hong Jan ,  Gopinath Bhimarasetti

IPC: H01L27/12 ,  H01L29/51 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/84 ,  H01L21/28 ,  H01L21/02 ,  H01L29/423

CPC classification number: H01L27/1211 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/02598 ,  H01L21/28158 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/845 ,  H01L29/42356 ,  H01L29/51 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6681

Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.

公开(公告)号：US09972616B2

公开(公告)日：2018-05-15

申请号：US14909980

申请日：2013-09-27

Applicant: INTEL CORPORATION

Inventor： Walid Hafez ,  Chen-Guan Lee ,  Chia-Hong Jan

IPC: H01L21/70 ,  H01L21/20 ,  H01L27/06 ,  H01L49/02 ,  H01L29/66 ,  H01L29/775 ,  H01C7/06 ,  H01C17/232

CPC classification number: H01L27/0629 ,  H01C7/06 ,  H01C17/232 ,  H01L28/20 ,  H01L28/24 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/775

Abstract: Methods of forming resistor structures with tunable temperature coefficient of resistance are described. Those methods and structures may include forming an opening in a resistor material adjacent source/drain openings on a device substrate, forming a dielectric material between the resistor material and the source/drain openings, and modifying the resistor material, wherein a temperature coefficient resistance (TCR) of the resistor material is tuned by the modification. The modifications include adjusting a length of the resistor, forming a compound resistor structure, and forming a replacement resistor.

公开(公告)号：US09899472B2

公开(公告)日：2018-02-20

申请号：US15409065

申请日：2017-01-18

Applicant: Intel Corporation

Inventor： Walid M. Hafez ,  Chia-Hong Jan

IPC: H01L29/80 ,  H01L29/06 ,  H01L27/098

CPC classification number: H01L29/0649 ,  H01L27/098 ,  H01L29/0657 ,  H01L29/404 ,  H01L29/66166 ,  H01L29/66803 ,  H01L29/66901 ,  H01L29/808 ,  H01L29/8605

Abstract: A dielectric and isolation lower fin material is described that is useful for fin-based electronics. In some examples, a dielectric layer is on first and second sidewalls of a lower fin. The dielectric layer has a first upper end portion laterally adjacent to the first sidewall of the lower fin and a second upper end portion laterally adjacent to the second sidewall of the lower fin. An isolation material is laterally adjacent to the dielectric layer directly on the first and second sidewalls of the lower fin and a gate electrode is over a top of and laterally adjacent to sidewalls of an upper fin. The gate electrode is over the first and second upper end portions of the dielectric layer and the isolation material.

公开(公告)号：US09799668B2

公开(公告)日：2017-10-24

申请号：US14779938

申请日：2013-06-25

Applicant: Intel Corporation

Inventor： Ting Chang ,  Chia-Hong Jan ,  Walid M. Hafez

IPC: H01L27/115 ,  H01L27/11563 ,  G11C16/04 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792

CPC classification number: H01L27/11563 ,  G11C16/0475 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/42348 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7923

Abstract: Memory cells having isolated charge sites and methods of fabricating memory cells having isolated charge sites are described. In an example, a nonvolatile charge trap memory device includes a substrate having a channel region, a source region and a drain region. A gate stack is disposed above the substrate, over the channel region. The gate stack includes a tunnel dielectric layer disposed above the channel region, a first charge-trapping region and a second charge-trapping region. The regions are disposed above the tunnel dielectric layer and separated by a distance. The gate stack also includes an isolating dielectric layer disposed above the tunnel dielectric layer and between the first charge-trapping region and the second charge-trapping region. A gate dielectric layer is disposed above the first charge-trapping region, the second charge-trapping region and the isolating dielectric layer. A gate electrode is disposed above the gate dielectric layer.

公开(公告)号：US09793373B2

公开(公告)日：2017-10-17

申请号：US15461427

申请日：2017-03-16

Applicant: Intel Corporation

Inventor： Anand S. Murthy ,  Robert S. Chau ,  Patrick Morrow ,  Chia-Hong Jan ,  Paul Packan

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/08 ,  H01L29/06 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L29/66636 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/2022 ,  H01L29/0646 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/41783 ,  H01L29/4925 ,  H01L29/66477 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7848

Abstract: Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer adjacent to the vertical sidewalls of the gate electrode, or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics. Alternative embodiments can be implemented with a back filled recess of a single conductivity type.

公开(公告)号：US09748252B2

公开(公告)日：2017-08-29

申请号：US14880814

申请日：2015-10-12

Applicant: INTEL CORPORATION

Inventor： Walid M. Hafez ,  Chia-Hong Jan ,  Curtis Tsai ,  Joodong Park ,  Jeng-Ya D. Yeh

IPC: H01L27/112 ,  H01L23/525 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L27/11206 ,  H01L21/823821 ,  H01L23/5252 ,  H01L27/0924 ,  H01L29/7853 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Techniques for providing non-volatile antifuse memory elements and other antifuse links are disclosed herein. In some embodiments, the antifuse memory elements are configured with non-planar topology such as FinFET topology. In some such embodiments, the fin topology can be manipulated and used to effectively promote lower breakdown voltage transistors, by creating enhanced-emission sites which are suitable for use in lower voltage non-volatile antifuse memory elements. In one example embodiment, a semiconductor antifuse device is provided that includes a non-planar diffusion area having a fin configured with a tapered portion, a dielectric isolation layer on the fin including the tapered portion, and a gate material on the dielectric isolation layer. The tapered portion of the fin may be formed, for instance, by oxidation, etching, and/or ablation, and in some cases includes a base region and a thinned region, and the thinned region is at least 50% thinner than the base region.