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    PROTECTED DATA ACCESSES USING REMOTE COPY OPERATIONS
    92.
    发明公开
    PROTECTED DATA ACCESSES USING REMOTE COPY OPERATIONS 审中-公开

    公开(公告)号：US20240111879A1

    公开(公告)日：2024-04-04

    申请号：US18370137

    申请日：2023-09-19

    Applicant: Intel Corporation

    Inventor： Ned SMITH ,  Kshitij A. DOSHI ,  Francesc GUIM BERNAT ,  Kapil SOOD ,  Tarun VISWANATHAN

    IPC: G06F21/60 ,  G06F15/173 ,  H04L9/32

    CPC classification number: G06F21/602 ,  G06F15/17331 ,  H04L9/3268

    Abstract: Examples herein relate to an interface selectively providing access to a memory region for a work request from an entity by providing selective access to a physical address of the memory region and selective access to a cryptographic key for use by a memory controller to access the memory region. In some examples, providing selective access to a physical address conversion is based on one or more of: validation of a certificate received with the work request and an identifier of the entity being associated with a process with access to the memory region. Access to the memory region can be specified to be one or more of: create, read, update, delete, write, or notify. A memory region can be a page or sub-page sized region. Different access rights can be associated with different sub-portions of the memory region, wherein the access rights comprise one or more of: create, read, update, delete, write, or notify.

    SELECTION OF PRIMARY AND SECONDARY MANAGEMENT CONTROLLERS IN A MULTIPLE MANAGEMENT CONTROLLER SYSTEM
    94.
    发明公开
    SELECTION OF PRIMARY AND SECONDARY MANAGEMENT CONTROLLERS IN A MULTIPLE MANAGEMENT CONTROLLER SYSTEM 审中-公开

    公开(公告)号：US20230375994A1

    公开(公告)日：2023-11-23

    申请号：US18228547

    申请日：2023-07-31

    Applicant: Intel Corporation

    Inventor： Francesc GUIM BERNAT ,  Eoin WALSH ,  Karthik KUMAR ,  Marcos E. CARRANZA

    IPC: G05B19/042

    CPC classification number: G05B19/042 ,  G05B2219/2214 ,  G05B2219/25022

    Abstract: Examples described herein relate to a system. In some examples, the system includes an interface and circuitry, coupled to the interface. In some examples, the circuitry, when operational, is to: based on detection of multiple management controllers, select a primary management controller and a secondary management controller from among the multiple management controllers. In some examples, the primary management controller is to perform at least one different operation than that of the secondary management controller, the primary management controller comprises a baseboard management controller (BMC), the secondary management controller comprises a BMC, and the multiple management controllers are positioned in at least one programmable network interface device and a host system.

    RAS (RELIABILITY, AVAILABILITY, AND SERVICEABILITY)-BASED MEMORY DOMAINS
    95.
    发明公开
    RAS (RELIABILITY, AVAILABILITY, AND SERVICEABILITY)-BASED MEMORY DOMAINS 审中-公开

    公开(公告)号：US20230222025A1

    公开(公告)日：2023-07-13

    申请号：US18124453

    申请日：2023-03-21

    Applicant: Intel Corporation

    Inventor： Karthik KUMAR ,  Francesc GUIM BERNAT ,  Mark A. SCHMISSEUR ,  Thomas WILLHALM ,  Marcos E. CARRANZA

    IPC: G06F11/00 ,  G06F11/14

    CPC classification number: G06F11/008 ,  G06F11/142

    Abstract: Reliability, availability, and serviceability (RAS)-based memory domains can enable applications to store data in memory domains having different degrees of reliability to reduce downtime and data corruption due to memory errors. In one example, memory resources are classified into different RAS-based memory domains based on their expected likelihood of encountering errors. The mapping of memory resources into RAS-based memory domains can be dynamically managed and updated when information indicative of reliability (such as the occurrence of errors or other information) suggests that a memory resource is becoming less reliable. The RAS-based memory domains can be exposed to applications to enable applications to allocate memory in high reliability memory for critical data.

    AUTONOMOUS RECOMMENDATION SYSTEM BASED ON ANONYMOUS DATA
    97.
    发明申请
    AUTONOMOUS RECOMMENDATION SYSTEM BASED ON ANONYMOUS DATA 有权

    公开(公告)号：US20220366478A1

    公开(公告)日：2022-11-17

    申请号：US17876596

    申请日：2022-07-29

    Applicant: Intel Corporation

    Inventor： Mario Jose DIVAN KOLLER ,  Marcos CARRANZA ,  Cesar MARTINEZ_SPESSOT ,  Mateo GUZMAN ,  Francesc GUIM BERNAT

    IPC: G06Q30/06 ,  G06F21/62

    Abstract: The application relates to an autonomous recommendation system, including: one or more BESs each configured to generate anonymous data representing customer-related information based on content streams from product-related cameras installed in a branch corresponding to the BES, and provide recommendation content to the branch based on the anonymous data; one or more ECSs each configured to aggregate the anonymous data from one or more BESs corresponding to respective branches in a region corresponding to the ECS to generate aggregated anonymous data shareable among regions corresponding to respective ECSs; and a DO configured to coordinate operations of the BESs and the ECSs based on predefined policies.

    SOFTWARE-ASSISTED SPARSE MEMORY
    99.
    发明申请
    SOFTWARE-ASSISTED SPARSE MEMORY 有权

    公开(公告)号：US20220318132A1

    公开(公告)日：2022-10-06

    申请号：US17847026

    申请日：2022-06-22

    Applicant: Intel Corporation

    Inventor： Thomas WILLHALM ,  Francesc GUIM BERNAT ,  Karthik KUMAR

    IPC: G06F12/02

    Abstract: Methods and apparatus for software-assisted sparse memory. A processor including a memory controller is configured to implement one or more portions of the memory space for memory accessed via the memory controller as sparse memory regions. The amount of physical memory used for a sparse memory region is a fraction of the address range for the sparse memory region, where only non-zero data are written to the physical memory. Mechanisms are provided to detect memory access requests for memory in a sparse memory region and perform associated operations, while non-sparse memory access operations are performed when accessing memory that is not in a sparse memory region. Interfaces are provided to enable software to request allocation of a new sparse memory region or allocate sparse memory from an existing sparse memory region. Operations associated with access to sparse memory regions include detecting whether data for read and write request are all zeros.

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