Semiconductor package with selective underfill and fabrication method therfor
    96.
    发明授权
    Semiconductor package with selective underfill and fabrication method therfor 有权
    具有选择性底部填充的半导体封装及其制造方法

    公开(公告)号:US07169641B2

    公开(公告)日:2007-01-30

    申请号:US11121847

    申请日:2005-05-03

    IPC分类号: H01L21/00

    摘要: A method of manufacturing a semiconductor package includes providing a substrate having a plurality of contacts with solder bump contact areas that are unmasked. A plurality of underfill bumps is formed on the plurality of contacts selectively in the solder bump contact areas. A die having a plurality of solder bumps is positioned on the substrate so the plurality of solder bumps is substantially vertically aligned with the plurality of underfill bumps. The plurality of solder bumps is pressed into the plurality of underfill bumps until the plurality of solder bumps contacts the plurality of contacts. The plurality of solder bumps is reflowed. The die, the plurality of solder bumps, and the plurality of contacts are encapsulated to expose a lower surface of the plurality of contacts.

    摘要翻译: 制造半导体封装的方法包括提供具有多个触点的衬底,该触点具有未被掩模的焊料凸块接触区域。 多个底部填充凸块在焊料凸块接触区域中选择性地形成在多个触点上。 具有多个焊料凸块的裸片位于衬底上,使得多个焊料凸块基本上与多个底部填充凸块垂直对齐。 多个焊料凸块被压入多个底部填充凸块中,直到多个焊料凸块接触多个触点。 多个焊料凸块被回流。 模具,多个焊料凸块和多个触点被封装以暴露多个触点的下表面。

    Cost effective substrate fabrication for flip-chip packages
    97.
    发明授权
    Cost effective substrate fabrication for flip-chip packages 有权
    用于倒装芯片封装的成本有效的衬底制造

    公开(公告)号:US06802445B2

    公开(公告)日:2004-10-12

    申请号:US10279900

    申请日:2002-10-24

    IPC分类号: B23K3102

    摘要: A new method is provided for the creation of high-accuracy and low-accuracy openings overlying points of electrical access over the surface of a semiconductor device supporting substrate. Openings are first created for access to the substrate followed by copper plating and then patterning of the plated layer of copper, creating the interconnect metal over the surface of the substrate. A first solder mask is coated over the surface of the substrate, this first solder mask must be provided with a first array of low-accuracy openings for electrical access there-through for the placement of contact balls. The first openings can be created using conventional film artwork since low accuracy is required for the contact ball openings, resulting in a low-cost process for the creation of the first openings. A second solder mask is next coated over the surface of the first solder mask. Through this second solder mask is created a second array of high-accuracy second openings that provide access to solder bumps using methods of laser ablation, resulting in a low-throughput process which however is only applied to create access to solder bumps.

    摘要翻译: 提供了一种新的方法,用于创建覆盖半导体器件支撑衬底的表面上的电接入点的高精度和低精度的开口。 首先创建开口用于进入基板,接着进行镀铜,然后对铜的镀层进行图案化,在基板的表面上形成互连金属。 第一焊接掩模涂覆在基板的表面上,该第一焊接掩模必须设置有第一阵列的低精度开口,用于电接入,用于放置接触球。 可以使用传统的胶片图案来创建第一开口,因为接触球开口需要低精度,导致用于产生第一开口的低成本工艺。 接下来将第二焊接掩模涂覆在第一焊接掩模的表面上。 通过该第二焊接掩模产生第二阵列的高精度第二开口,其使用激光烧蚀的方法提供对焊料凸点的接近,导致低通量过程,然而其仅用于形成对焊料凸点的访问。

    Multi-stacked memory package
    99.
    发明授权
    Multi-stacked memory package 有权
    多堆叠内存包

    公开(公告)号:US06683377B1

    公开(公告)日:2004-01-27

    申请号:US09583183

    申请日:2000-05-30

    IPC分类号: H01L2334

    摘要: A multiple chip package and method of making the package allow multiple same size or different size chips to be stacked over each other, thereby creating a thin profile multi-chip package. Chips are attached to one surface of a continuous flexible substrate. The substrate has a metallization layer, which is electrically connected to the chips, such as via bond wires attached to center bond pads of the chips and to bond fingers on the metallization layer. Interconnections, such as solder balls, are attached to the other surface of the substrate and only at the portion opposite to the first chip. The substrate is folded to bring the first chip toward a second chip, which are then attached, such as with an insulative adhesive spacer. If any additional chips remain on the substrate, the substrate is folded to sequentially bring each additional chip toward the surface of the substrate opposite to the preceding chip and is secured thereto.

    摘要翻译: 制造封装的多芯片封装和方法允许多个相同尺寸或​​不同尺寸的芯片彼此堆叠,从而形成薄型多芯片封装。 芯片连接到连续柔性基板的一个表面。 衬底具有电连接到芯片的金属化层,例如连接到芯片的中心接合焊盘的通孔接合线,并且在金属化层上粘合指状物。 诸如焊球之类的互连连接到衬底的另一表面,并且仅在与第一芯片相对的部分处。 将基板折叠以将第一芯片朝向第二芯片,然后将其连接,例如用绝缘粘合剂间隔件。 如果在基板上剩余另外的芯片,则将基板折叠成顺序地使每个附加芯片朝向与先前芯片相对的基板的表面并固定到其上。