公开(公告)号：US20250118693A1

公开(公告)日：2025-04-10

申请号：US18776197

申请日：2024-07-17

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Kunal R. Parekh ,  Akshay N. Singh

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/498 ,  H01L25/18 ,  H10B80/00

Abstract: Methods, systems, and devices for techniques for semiconductor die coupling in stacked memory architectures are described. A semiconductor system may include a semiconductor unit formed by multiple semiconductor dies, where each semiconductor die may be fabricated to be individually separable. Each semiconductor die may include a respective portion of circuitry associated with the semiconductor unit. The multiple semiconductor dies may be coupled with a carrier, and each semiconductor die may be coupled (e.g., electrically, communicatively) with at least one other semiconductor die. At least some of the semiconductor dies may be coupled with a respective set of one or more memory arrays, where each memory array may be operable based on the coupling between the multiple semiconductor dies.

公开(公告)号：US12261111B2

公开(公告)日：2025-03-25

申请号：US18600146

申请日：2024-03-08

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh

IPC: H01L23/522 ,  G11C7/18 ,  H01L23/00 ,  H01L23/528 ,  H01L25/18 ,  H10B41/27 ,  H10B41/35

Abstract: A method of forming a microelectronic device comprises forming a microelectronic device structure comprising a base structure, a doped semiconductive material overlying the base structure, a stack structure overlying the doped semiconductive material, cell pillar structures vertically extending through the stack structure and the doped semiconductive material and into the base structure, and digit line structures vertically overlying the stack structure. An additional microelectronic device structure comprising control logic devices is formed. The microelectronic device structure is attached to the additional microelectronic device structure to form a microelectronic device structure assembly. The base structure and portions of the cell pillar structures vertically extending into the base structure are removed to expose the doped semiconductive material. The doped semiconductive material is then patterned to form at least one source structure over the stack structure and coupled to the cell pillar structures. Microelectronic devices and electronic systems are also described.

公开(公告)号：US20250006251A1

公开(公告)日：2025-01-02

申请号：US18829647

申请日：2024-09-10

Applicant: Micron Technology, Inc.

Inventor： Aliasger T. Zaidy ,  Glen E. Hush ,  Sean S. Eilert ,  Kunal R. Parekh

IPC: G11C11/4093 ,  G06F3/06 ,  G06F13/16 ,  G06F13/28 ,  G11C7/08 ,  G11C7/10 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4096 ,  G16B30/00 ,  G16B50/10 ,  H01L21/66 ,  H01L21/78 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

Abstract: A memory device includes a memory die bonded to a logic die. A logic die that is bonded to a memory die via a wafer-on-wafer bonding process can receive signals indicative of input data from a global data bus of the memory die and through a bond of the logic die and memory die. The logic die can also receive signals indicative of kernel data from local input/output (LIO) lines of the memory die and through the bond. The logic die can perform a plurality of operations at a plurality of vector-vector (VV) units utilizing the signals indicative of input data and the signals indicative of kernel data. The inputs and the outputs to the VV units can be configured based on a mode of the logic die.

公开(公告)号：US20240379596A1

公开(公告)日：2024-11-14

申请号：US18660210

申请日：2024-05-09

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Terrence B. McDaniel ,  Kunal R. Parekh ,  Bret K. Street ,  Akshay N. Singh

IPC: H01L23/00 ,  H01L21/311 ,  H01L23/48 ,  H01L25/065

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate having a front side and a back side opposite the front side. A through via extends entirely through the substrate. The through via includes a protruding portion that extends beyond the back side of the substrate. A layer of silicon carbon nitride is disposed at the back side of the substrate and along sidewalls of the protruding portion of the through via. A layer of oxide is disposed at the back side of the substrate and at least partially surrounding the protruding portion of the through via. A conductive pad is disposed at a coupling surface of the through via and at least partially extending through the layer of oxide. As a result, a reliable and cost-efficient semiconductor device can be assembled.

公开(公告)号：US20240315018A1

公开(公告)日：2024-09-19

申请号：US18676056

申请日：2024-05-28

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Kunal R. Parekh ,  Martin C. Roberts ,  Mohd Kamran Akhtar ,  Chet E. Carter ,  David Daycock

IPC: H10B41/35 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3215 ,  H01L21/67 ,  H01L21/768 ,  H10B20/00 ,  H10B41/20 ,  H10B41/23 ,  H10B41/27 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B41/35 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/3215 ,  H01L21/32155 ,  H01L21/67063 ,  H01L21/76802 ,  H10B20/383 ,  H10B41/20 ,  H10B41/23 ,  H10B41/27 ,  H10B43/27 ,  H01L2221/1063 ,  H10B43/35

Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US12096626B2

公开(公告)日：2024-09-17

申请号：US18149318

申请日：2023-01-03

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh

IPC: H10B41/27 ,  G11C5/02 ,  G11C5/06 ,  H01L23/522 ,  H01L23/532 ,  H10B43/27

CPC classification number: H10B41/27 ,  G11C5/025 ,  G11C5/06 ,  H01L23/5226 ,  H01L23/53214 ,  H01L23/53228 ,  H10B43/27

Abstract: A microelectronic device comprises a memory array region, a control logic region underlying the memory array region, and an interconnect region vertically interposed between the memory array region and the control logic region. The memory array region comprises a stack structure comprising vertically alternating conductive structures and insulating structures; vertically extending strings of memory cells within the stack structure; at least one source structure vertically overlying the stack structure and coupled to the vertically extending strings of memory cells; and digit line structures vertically underlying the stack structure and coupled to the vertically extending strings of memory cells. The control logic region comprises control logic devices for the vertically extending strings of memory cells. The interconnect region comprises structures coupling the digit line structures to the control logic devices. Methods of forming a microelectronic device, and memory devices and electronic systems are also described.

公开(公告)号：US12080700B2

公开(公告)日：2024-09-03

申请号：US18147342

申请日：2022-12-28

Applicant: Micron Technology, Inc.

Inventor： Aaron S. Yip ,  Kunal R. Parekh ,  Akira Goda

IPC: H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L25/18 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06524 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A microelectronic device comprises a first die comprising a memory array region comprising a stack structure comprising vertically alternating conductive structures and insulative structures, and vertically extending strings of memory cells within the stack structure. The first die further comprises a first control logic region comprising a first control logic device including at least a word line driver. The microelectronic device further comprises a second die attached to the first die, the second die comprising a second control logic region comprising second control logic devices including at least one page buffer device configured to effectuate a portion of control operations of the vertically extending string of memory cells. Related microelectronic devices, electronic systems, and methods are also described.

公开(公告)号：US12074094B2

公开(公告)日：2024-08-27

申请号：US17670378

申请日：2022-02-11

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Kyle K. Kirby ,  Bret K. Street ,  Kunal R. Parekh

IPC: H01L21/00 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L23/481 ,  H01L21/76877 ,  H01L21/76898 ,  H01L24/08 ,  H01L24/32 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/08146 ,  H01L2224/32145 ,  H01L2224/8319 ,  H01L2225/06541

Abstract: A semiconductor device having monolithic conductive columns, and associated systems and methods, are disclosed herein. The semiconductor device can include a semiconductor substrate, a conductive pad, an opening, a non-conductive liner, and a plug of non-conductive material. The conductive pad may be at a surface of the semiconductor substrate. The opening may extend through the semiconductor substrate from the conductive pad to a second surface and define a side wall. The liner may coat the side wall and the plug may fill the opening. A second opening may be formed through the semiconductor device and the opening and a conductive material plated therein.

公开(公告)号：US20240237363A1

公开(公告)日：2024-07-11

申请号：US18400994

申请日：2023-12-29

Applicant: Micron Technology, Inc.

Inventor： James Brian Johnson ,  Brent Keeth ,  Ameen D. Akel ,  Kunal R. Parekh ,  Amy Rae Griffin ,  Eiichi Nakano

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H10B80/00 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/1434

Abstract: Methods, systems, and devices for modular die configurations for multi-channel memory are described. A semiconductor component (e.g., a semiconductor wafer) may be configured with multiple rows and multiple columns of memory arrays, and associated channels. A row of memory arrays may be associated with a contact region extending along the row direction. The semiconductor component may also include control regions extending along the column direction between at least some of the columns of memory arrays. Each control region may include control circuitry for operating memory arrays on one or both sides of the control region. The channels and memory arrays of the semiconductor wafer may be grouped into one or more independently-operable memory dies, with each memory die having at least a portion of a control region and at least a portion of a contact region for operating the memory arrays of the memory die.

公开(公告)号：US11929323B2

公开(公告)日：2024-03-12

申请号：US18175398

申请日：2023-02-27

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh

IPC: H01L23/522 ,  G11C7/18 ,  H01L23/00 ,  H01L23/528 ,  H01L25/18 ,  H10B41/27 ,  H10B41/35

CPC classification number: H01L23/5226 ,  G11C7/18 ,  H01L23/5283 ,  H01L24/05 ,  H01L25/18 ,  H10B41/27 ,  H10B41/35 ,  H01L2924/1431 ,  H01L2924/1443

Abstract: A method of forming a microelectronic device comprises forming a microelectronic device structure comprising a base structure, a doped semiconductive material overlying the base structure, a stack structure overlying the doped semiconductive material, cell pillar structures vertically extending through the stack structure and the doped semiconductive material and into the base structure, and digit line structures vertically overlying the stack structure. An additional microelectronic device structure comprising control logic devices is formed. The microelectronic device structure is attached to the additional microelectronic device structure to form a microelectronic device structure assembly. The base structure and portions of the cell pillar structures vertically extending into the base structure are removed to expose the doped semiconductive material. The doped semiconductive material is then patterned to form at least one source structure over the stack structure and coupled to the cell pillar structures. Microelectronic devices and electronic systems are also described.