公开(公告)号：US20200335487A1

公开(公告)日：2020-10-22

申请号：US16917526

申请日：2020-06-30

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Adarsh RAJASHEKHAR ,  Raghuveer S. MAKALA ,  Fei ZHOU

IPC: H01L25/18 ,  H01L29/04 ,  H01L29/16 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00

Abstract: A semiconductor structure includes a memory die bonded to a support die. The memory die includes an alternating stack of insulating layers and electrically conductive layers located over a first single crystalline semiconductor layer, and memory stack structures extending through the alternating stack and containing respective memory film and a respective vertical semiconductor channel including a single crystalline channel semiconductor material. The support die includes a peripheral circuitry.

公开(公告)号：US20200286907A1

公开(公告)日：2020-09-10

申请号：US16882957

申请日：2020-05-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Chun GE ,  Yanli ZHANG ,  Fei ZHOU ,  Raghuveer S. MAKALA

IPC: H01L27/11568 ,  H01L29/51 ,  H01L29/792 ,  H01L27/1159 ,  H01L29/78 ,  H01L21/28 ,  H01L29/423

Abstract: A combination of an alternating stack and a memory opening fill structure is provided over a substrate. The alternating stack includes insulating layers and electrically conductive layers. The memory opening fill structure vertically extends through the alternating stack, and includes a memory film, a vertical semiconductor channel, and a core structure comprising a core material. A phase change material is employed for the core material. A volume expansion is induced in in the core material by performing an anneal process that induces a microstructural change within the core material. The volume expansion in the core material induces a lateral compressive strain and a vertical tensile strain within the vertical semiconductor channel. The vertical tensile strain enhances charge mobility in the vertical semiconductor channel, and increases the on-current of the vertical semiconductor channel.

公开(公告)号：US20200152655A1

公开(公告)日：2020-05-14

申请号：US16183920

申请日：2018-11-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Fei ZHOU ,  Raghuveer S. MAKALA ,  Adarsh RAJASHEKHAR

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L21/768

Abstract: A vertical repetition of a unit layer stack including an insulating layer, a sacrificial material layer, and a nucleation promoter layer is formed over a substrate. Memory stack structures are formed through the vertical repetition. Each of the memory stack structures comprises a memory film and a vertical semiconductor channel. Backside recesses are formed by removing the sacrificial material layers selective to the insulating layers and the nucleation promoter layers within the vertical repetition. Electrically conductive layers are formed in the backside recesses by selectively growing a metallic material from physically exposed surfaces of the nucleation promoter layers while suppressing growth of the metallic material from physically exposed surfaces of the insulating layers.

公开(公告)号：US20190148506A1

公开(公告)日：2019-05-16

申请号：US15813579

申请日：2017-11-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Senaka Krishna KANAKAMEDALA ,  Yoshihiro KANNO ,  Raghuveer S. MAKALA ,  Yanli ZHANG ,  Jin LIU ,  Murshed CHOWDHURY ,  Yao-Sheng LEE

IPC: H01L29/423 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/522 ,  H01L29/66 ,  H01L29/49

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. Memory stack structures are located in a memory array region, each of which includes a memory film and a vertical semiconductor channel. Contact via structures located in the terrace region and contact a respective one of the electrically conductive layers. Each of the electrically conductive layers has a respective first thickness throughout the memory array region and includes a contact portion having a respective second thickness that is greater than the respective first thickness within a terrace region. The greater thickness of the contact portion prevents an etch-through during formation of contact via cavities for forming the contact via structures.

公开(公告)号：US20180151497A1

公开(公告)日：2018-05-31

申请号：US15581575

申请日：2017-04-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Raghuveer S. MAKALA ,  Murshed CHOWDHURY ,  Keerti SHUKLA ,  Tomohisa ABE ,  Yao-Sheng LEE ,  James KAI

IPC: H01L23/535 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11565 ,  H01L29/167 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76889 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L27/0688 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/167

Abstract: A three-dimensional memory device includes driver transistors containing boron doped semiconductor active regions, device contact via structures in physical contact with the boron doped semiconductor active regions, the device contact via structures containing at least one of tantalum, tungsten, and cobalt, and a three-dimensional memory array located over the driver transistors and including an alternating stack of insulating layers and electrically conductive layers and memory structures vertically extending through the alternating stack.

公开(公告)号：US20170278859A1

公开(公告)日：2017-09-28

申请号：US15250185

申请日：2016-08-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Senaka KANAKAMEDALA ,  Fei ZHOU ,  Somesh PERI ,  Masanori TSUTSUMI ,  Keerti SHUKLA ,  Yusuke IKAWA ,  Kiyohiko SAKAKIBARA ,  Eisuke TAKII

IPC: H01L27/115 ,  H01L21/02 ,  H01L29/51

CPC classification number: H01L27/11582 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02247 ,  H01L21/02326 ,  H01L21/31111 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

Abstract: A memory opening can be formed through an alternating stack of insulating layers and sacrificial material layers provided over a substrate. Annular etch stop material portions are provided at each level of the sacrificial material layers around the memory opening. The annular etch stop material portions can be formed by conversion of surface portions of the sacrificial material layers into dielectric material portion, or by recessing the sacrificial material layers around the memory opening and filling indentations around the memory opening. After formation of a memory stack structure, the sacrificial material layers are removed from the backside. The annular etch stop material portions are at least partially converted to form charge trapping material portions. Vertical isolation of the charge trapping material portions among one another around the memory stack structure minimizes leakage between the charge trapping material portions located at different word line levels.

公开(公告)号：US20240290622A1

公开(公告)日：2024-08-29

申请号：US18359664

申请日：2023-07-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Roshan Jayakhar TIRUKKONDA ,  Rahul SHARANGPANI ,  Senaka KANAKAMEDALA ,  Raghuveer S. MAKALA

IPC: H01L21/306 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L21/30608 ,  H01L21/76876 ,  H01L23/5226 ,  H01L23/5283 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A method includes forming an alternating stack of first material layers and second material layers over a substrate, forming an etch mask material layer over the alternating stack, loading the etch mask material layer, the alternating stack, and the substrate into an integrated processing apparatus including a plurality of etch chambers and at least one cladding liner deposition chamber; and iteratively performing multiple instances of a unit processing sequence without breaking vacuum. The unit processing sequence includes a respective cladding liner deposition process in which a respective cladding material is anisotropically deposited over the etch mask material layer in a respective one of the at least one cladding liner deposition chamber, and a respective anisotropic etch process in which respective portions of the alternating stack that are not masked by the etch mask material layer are anisotropically etched in a respective etch chamber selected from the plurality of etch chambers.

公开(公告)号：US20240237355A9

公开(公告)日：2024-07-11

申请号：US18350524

申请日：2023-07-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Bing ZHOU ,  Monica TITUS ,  Raghuveer S. MAKALA ,  Rahul SHARANGPANI ,  Senaka KANAKAMEDALA

IPC: H10B43/35 ,  G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B43/35 ,  G11C16/0483 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27

Abstract: A etch stop structure is formed a sacrificial memory opening fill structure formed within a first-tier memory opening vertically extending through a first-tier alternating stack of first insulating layers and first spacer material layers. The etch stop structure may include a conductive etch stop plate that is formed over a sacrificial memory opening fill material portion inside the first-tier memory opening, or may include a semiconductor plug which is selectively grown from sidewalls of an etch stop semiconductor material layer that is formed over the first-tier alternating stack. A second-tier alternating stack of second insulating layers and second spacer material layers is formed over the first-tier alternating stack and the etch stop structure.

公开(公告)号：US20240138151A1

公开(公告)日：2024-04-25

申请号：US18350524

申请日：2023-07-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Bing ZHOU ,  Monica TITUS ,  Raghuveer S. MAKALA ,  Rahul SHARANGPANI ,  Senaka KANAKAMEDALA

IPC: H10B43/35 ,  G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B43/35 ,  G11C16/0483 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27

Abstract: A etch stop structure is formed a sacrificial memory opening fill structure formed within a first-tier memory opening vertically extending through a first-tier alternating stack of first insulating layers and first spacer material layers. The etch stop structure may include a conductive etch stop plate that is formed over a sacrificial memory opening fill material portion inside the first-tier memory opening, or may include a semiconductor plug which is selectively grown from sidewalls of an etch stop semiconductor material layer that is formed over the first-tier alternating stack. A second-tier alternating stack of second insulating layers and second spacer material layers is formed over the first-tier alternating stack and the etch stop structure.

公开(公告)号：US20240121960A1

公开(公告)日：2024-04-11

申请号：US18348702

申请日：2023-07-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Adarsh RAJASHEKHAR ,  Raghuveer S. MAKALA ,  Fei ZHOU ,  Rahul SHARANGPANI ,  Kartik SONDHI

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack and having a lateral undulation in a vertical cross-sectional profile such that the memory opening laterally protrudes outward at levels of the electrically conductive layers, and a memory opening fill structure located in the memory opening and including a vertical stack of blocking dielectric material portions located at the levels of the electrically conductive layers, a vertical stack of discrete memory elements located at the levels of the electrically conductive layers and including a respective contoured charge storage material portion, a tunneling dielectric layer overlying the contoured inner sidewalls of the tubular charge storage material portion, and a vertical semiconductor channel.