公开(公告)号：US07354812B2

公开(公告)日：2008-04-08

申请号：US10931946

申请日：2004-09-01

申请人： Shubneesh Batra ,  Howard C. Kirsch ,  Gurtej S. Sandhu ,  Xianfeng Zhou ,  Chih-Chen Cho

发明人： Shubneesh Batra ,  Howard C. Kirsch ,  Gurtej S. Sandhu ,  Xianfeng Zhou ,  Chih-Chen Cho

IPC分类号： H01L21/337 ,  H01L21/8238 ,  H01L21/8249 ,  H01L21/336 ,  H01L21/331 ,  H01L21/76 ,  H01L33/00 ,  H01L29/76 ,  H01L31/00 ,  H01L29/00

CPC分类号： H01L21/76229

摘要： Multiple trench depths within an integrated circuit device are formed by first forming trenches in a substrate to a first depth, but of varying widths. Formation of a dielectric layer can cause some of the trenches to fill or close off while leaving other, wider trenches open. Removal of a portion of the dielectric material can then be tailored to expose a bottom of the open trenches while leaving remaining trenches filled. Removal of exposed portions of the underlying substrate can then be used to selectively deepen the open trenches, which can subsequently be filled. Such methods can be used to form trenches of varying depths without the need for subsequent masking.

摘要翻译： 集成电路器件内的多个沟槽深度通过首先将衬底中的沟槽形成第一深度但具有变化的宽度来形成。 电介质层的形成可以使一些沟槽填充或封闭，同时留下其他更宽的沟槽打开。 然后可以去除电介质材料的一部分以暴露开口沟槽的底部，同时留下剩余的沟槽填充。 然后可以去除下面的衬底的暴露部分以选择性地加深可以随后填充的开放沟槽。 这种方法可用于形成不同深度的沟槽，而不需要随后的掩蔽。

公开(公告)号：US07352023B2

公开(公告)日：2008-04-01

申请号：US11485592

申请日：2006-07-11

申请人： Cem Basceri ,  F. Daniel Gealy ,  Gurtej S. Sandhu

发明人： Cem Basceri ,  F. Daniel Gealy ,  Gurtej S. Sandhu

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01G4/33 ,  H01G4/1209 ,  H01G4/1272 ,  H01L21/31645 ,  H01L27/10852 ,  H01L28/60 ,  H01L28/65 ,  H01L28/90 ,  H01L28/91 ,  H01L29/7833

摘要： The invention includes methods of forming hafnium-containing materials, such as, for example, hafnium oxide. In one aspect, a semiconductor substrate is provided, and first reaction conditions are utilized to form hafnium-containing seed material in a desired crystalline phase and orientation over the substrate. Subsequently, second reaction conditions are utilized to grow second hafnium-containing material over the seed material. The second hafnium-containing material is in a crystalline phase and/or orientation different from the crystalline phase and orientation of the hafnium-containing seed material. The second hafnium-containing material can be, for example, in an amorphous phase. The seed material is then utilized to induce a desired crystalline phase and orientation in the second hafnium-containing material. The invention also includes capacitor constructions utilizing hafnium-containing materials, and circuit assemblies comprising the capacitor constructions.

摘要翻译： 本发明包括形成含铪材料的方法，例如氧化铪。 在一个方面，提供了半导体衬底，并且利用第一反应条件来形成在衬底上所需的结晶相和取向的含铪种子材料。 随后，利用第二反应条件在种子材料上生长第二含铪材料。 第二含铪材料处于与含铪种子材料的结晶相和取向不同的结晶相和/或取向。 第二含铪材料可以是例如非晶相。 然后将种子材料用于在第二含铪材料中诱导所需的结晶相和取向。 本发明还包括使用含铪材料的电容器结构和包括电容器结构的电路组件。

公开(公告)号：US07344975B2

公开(公告)日：2008-03-18

申请号：US11213283

申请日：2005-08-26

申请人： Gurtej S. Sandhu ,  Max F. Hineman ,  Daniel A. Steckert ,  Jingyi Bai ,  Shane J. Trapp ,  Tony Schrock

发明人： Gurtej S. Sandhu ,  Max F. Hineman ,  Daniel A. Steckert ,  Jingyi Bai ,  Shane J. Trapp ,  Tony Schrock

IPC分类号： H01L21/4763

CPC分类号： H01L21/76802 ,  H01L21/31116 ,  Y10S438/906

摘要： A method of high aspect ratio contact etching a substantially vertical contact hole in an oxide layer using a hard photoresist mask is described. The oxide layer is deposited on an underlying substrate. A plasma etching gas is formed from a carbon source gas. Dopants are mixed into the gas. The doped plasma etching gas etches a substantially vertical contact hole through the oxide layer by doping carbon chain polymers formed along the sidewalls of the contact holes during the etching process into a conductive state. The conductive state of the carbon chain polymers reduces the charge buildup along sidewalls to prevent twisting of the contact holes by bleeding off the charge and ensuring proper alignment with active area landing regions. The etching stops at the underlying substrate.

摘要翻译： 描述了使用硬光致抗蚀剂掩模的高纵横比接触蚀刻氧化物层中的基本上垂直的接触孔的方法。 氧化物层沉积在下面的衬底上。 由碳源气体形成等离子体蚀刻气体。 掺杂剂混入气体中。 掺杂的等离子体蚀刻气体通过在蚀刻工艺期间将沿着接触孔的侧壁形成的碳链聚合物掺杂到导电状态来蚀刻通过氧化物层的基本垂直的接触孔。 碳链聚合物的导电状态减少了沿着侧壁的电荷累积，以防止通过渗出电荷并确保与有源区着陆区域的适当对准来接合孔的扭曲。 蚀刻停止在下面的基底。

公开(公告)号：US07344948B2

公开(公告)日：2008-03-18

申请号：US10050347

申请日：2002-01-15

申请人： Gurtej S. Sandhu ,  John T. Moore ,  Neal R. Rueger

发明人： Gurtej S. Sandhu ,  John T. Moore ,  Neal R. Rueger

IPC分类号： H01L21/4763

CPC分类号： H01L21/02332 ,  H01L21/0234 ,  H01L21/265 ,  H01L21/28061 ,  H01L21/28167 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/3144 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

摘要： The invention encompasses a method of incorporating nitrogen into a silicon-oxide-containing layer. The silicon-oxide-containing layer is exposed to a nitrogen-containing plasma to introduce nitrogen into the layer. The nitrogen is subsequently thermally annealed within the layer to bond at least some of the nitrogen to silicon within the layer. The invention also encompasses a method of forming a transistor. A gate oxide layer is formed over a semiconductive substrate. The gate oxide layer comprises silicon dioxide. The gate oxide layer is exposed to a nitrogen-containing plasma to introduce nitrogen into the layer, and the layer is maintained at less than or equal to 400° C. during the exposing. Subsequently, the nitrogen within the layer is thermally annealed to bond at least a majority of the nitrogen to silicon. At least one conductive layer is formed over the gate oxide layer. Source/drain regions are formed within the semiconductive substrate, and are gatedly connected to one another by the at least one conductive layer. The invention also encompasses transistor structures.

摘要翻译： 本发明包括将氮掺入含氧化硅的层中的方法。 将含氧化硅的层暴露于含氮等离子体中以将氮引入层中。 氮气随后在层内热退火以将至少一些氮与硅结合在层内。 本发明还包括形成晶体管的方法。 在半导体衬底上形成栅氧化层。 栅氧化层包括二氧化硅。 将栅极氧化层暴露于含氮等离子体中以将氮引入层中，并且在暴露期间该层保持在小于或等于400℃。 随后，层内的氮被热退火以将至少大部分氮与硅结合。 在栅极氧化物层上形成至少一个导电层。 源极/漏极区域形成在半导体衬底内，并且通过至少一个导电层彼此门控连接。 本发明还包括晶体管结构。

公开(公告)号：US20080038933A1

公开(公告)日：2008-02-14

申请号：US11503762

申请日：2006-08-14

申请人： Neal R. Rueger ,  Mark J. Williamson ,  Gurtej S. Sandhu

发明人： Neal R. Rueger ,  Mark J. Williamson ,  Gurtej S. Sandhu

IPC分类号： H01L21/31

CPC分类号： H01L21/31116 ,  C23C16/0245 ,  C23C16/042 ,  C23C16/26 ,  C23C16/517 ,  H01J37/28 ,  H01J37/3178 ,  H01J37/3233 ,  H01J2237/2605 ,  H01J2237/3137 ,  H01J2237/3151 ,  H01J2237/31732 ,  H01J2237/3174 ,  H01L27/1052 ,  Y10S438/905 ,  Y10S438/909

摘要： Methods and devices for selective etching in a semiconductor process are shown. Chemical species generated in a reaction chamber provide both a selective etching function and concurrently form a protective coating on other regions. An electron beam provides activation to selective chemical species. In one example, reactive species are generated from a plasma source to provide an increased reactive species density. Addition of other gasses to the system can provide functions such as controlling a chemistry in a protective layer during a processing operation.

摘要翻译： 示出了在半导体工艺中选择性蚀刻的方法和装置。 在反应室中产生的化学物质既提供选择性蚀刻功能又在其它区域形成保护涂层。 电子束为选择性化学物质提供活化。 在一个实例中，从等离子体源产生反应性物质以提供增加的反应物种密度。 在系统中添加其他气体可以提供诸如在处理操作期间控制保护层中的化学物质的功能。

公开(公告)号：US07329576B2

公开(公告)日：2008-02-12

申请号：US11021639

申请日：2004-12-22

申请人： Gurtej S. Sandhu ,  Kevin R. Shea ,  Chris W. Hill ,  Kevin J. Torek

发明人： Gurtej S. Sandhu ,  Kevin R. Shea ,  Chris W. Hill ,  Kevin J. Torek

IPC分类号： H01L21/8242

CPC分类号： H01L28/91 ,  H01L27/10852

摘要： Double-sided container capacitors are formed using sacrificial layers. A sacrificial layer is formed within a recess in a structural layer. A lower electrode is formed within the recess. The sacrificial layer is removed to create a space to allow access to the sides of the structural layer. The structural layer is removed, creating an isolated lower electrode. The lower electrode can be covered with a capacitor dielectric and upper electrode to form a double-sided container capacitor.

摘要翻译： 使用牺牲层形成双面容器电容器。 在结构层的凹部内形成牺牲层。 下部电极形成在凹部内。 去除牺牲层以产生允许接近结构层的侧面的空间。 去除结构层，形成隔离的下电极。 下电极可以用电容器电介质和上电极覆盖以形成双面容器电容器。

公开(公告)号：US07323737B2

公开(公告)日：2008-01-29

申请号：US11517209

申请日：2006-09-06

申请人： Cem Basceri ,  F. Daniel Gealy ,  Gurtej S. Sandhu

发明人： Cem Basceri ,  F. Daniel Gealy ,  Gurtej S. Sandhu

IPC分类号： H01L27/108 ,  H01L23/48 ,  H01L21/8234

CPC分类号： H01L27/10855 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/57

摘要： The invention includes methods in which metal oxide dielectric materials are deposited over barrier layers. The barrier layers can comprise compositions of metal and one or more of carbon, boron and nitrogen, and the metal oxide of the dielectric material can comprise the same metal as the barrier layer. The dielectric material/barrier layer constructions can be incorporated into capacitors. The capacitors can be used in, for example, DRAM cells, which in turn can be used in electronic systems.

摘要翻译： 本发明包括其中金属氧化物电介质材料沉积在阻挡层上的方法。 阻挡层可以包括金属和碳，硼和氮中的一种或多种的组合物，并且介电材料的金属氧化物可以包含与阻挡层相同的金属。 电介质材料/阻挡层结构可以结合到电容器中。 电容器可以用在例如DRAM单元中，DRAM单元又可以用在电子系统中。

公开(公告)号：US20070281220A1

公开(公告)日：2007-12-06

申请号：US11445907

申请日：2006-06-02

申请人： Gurtej S. Sandhu ,  Steve Kramer

发明人： Gurtej S. Sandhu ,  Steve Kramer

IPC分类号： G03F7/26

CPC分类号： H01L21/0337 ,  H01L21/0332 ,  H01L21/0338 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/3088

摘要： A mask having features formed by self-organizing material, such as diblock copolymers, is formed on a partially fabricated integrated circuit. Initially, a copolymer template, or seed layer, is formed on the surface of the partially fabricated integrated circuit. To form the seed layer, diblock copolymers, composed of two immiscible blocks, are deposited in the space between copolymer alignment guides. The copolymers are made to self-organize, with the guides guiding the self-organization and with each block aggregating with other blocks of the same type, thereby forming the seed layer. Next, additional, supplemental diblock copolymers are deposited over the seed layer. The copolymers in the seed layer guide self-organization of the supplemental copolymers, thereby vertically extending the pattern formed by the copolymers in the seed layer. Block species are subsequently selectively removed to form a pattern of voids defined by the remaining block species, which form a mask that can be used to pattern an underlying substrate. The supplemental copolymers augment the height of the copolymers in the seed layer, thereby facilitating the use of the copolymers for patterning the underlying substrate.

摘要翻译： 在部分制造的集成电路上形成具有由诸如二嵌段共聚物之类的自组织材料形成的特征的掩模。 最初，在部分制造的集成电路的表面上形成共聚物模板或种子层。 为了形成种子层，由共混物对准引导件之间的空间中沉积由两个不混溶的嵌段组成的二嵌段共聚物。 使共聚物自组织，引导引导自组织，每个块与相同类型的其它嵌段聚集，从而形成种子层。 接下来，在种子层上沉积另外的补充二嵌段共聚物。 种子层中的共聚物引导辅助共聚物的自组织，从而在种子层中垂直延伸由共聚物形成的图案。 随后选择性地去除块物质以形成由剩余的嵌段物质限定的空隙图案，其形成可用于对下面的基底进行图案化的掩模。 补充共聚物增加了种子层中共聚物的高度，从而有利于共聚物用于图案化下面的底物。

公开(公告)号：US07303991B2

公开(公告)日：2007-12-04

申请号：US10863048

申请日：2004-06-07

申请人： Demetrius Sarigiannis ,  Garo J. Derderian ,  Cem Basceri ,  Gurtej S. Sandhu ,  F. Daniel Gealy ,  Chris M. Carlson

发明人： Demetrius Sarigiannis ,  Garo J. Derderian ,  Cem Basceri ,  Gurtej S. Sandhu ,  F. Daniel Gealy ,  Chris M. Carlson

IPC分类号： H01L21/44

CPC分类号： H01L21/32051 ,  C23C16/4404 ,  C23C16/4405 ,  C23C16/45531 ,  C23C16/45534 ,  H01L21/02178 ,  H01L21/02186 ,  H01L21/0228 ,  H01L21/28562 ,  H01L21/3141 ,  H01L21/31616

摘要： The invention includes an atomic layer deposition method of forming a layer of a deposited composition on a substrate. The method includes positioning a semiconductor substrate within an atomic layer deposition chamber. On the substrate, an intermediate composition monolayer is formed, followed by a desired deposited composition from reaction with the intermediate composition, collectively from flowing multiple different composition deposition precursors to the substrate within the deposition chamber. A material adheres to a chamber internal component surface from such sequentially forming. After such sequentially forming, a reactive gas flows to the chamber which is different in composition from the multiple different deposition precursors and which is effective to react with such adhering material. After the reactive gas flowing, such sequentially forming is repeated. Further implementations are contemplated.

摘要翻译： 本发明包括在基板上形成沉积的组合物层的原子层沉积方法。 该方法包括将半导体衬底定位在原子层沉积室内。 在基材上形成中间体组合物单层，随后是与中间体组合物反应所需的沉积组合物，共同地将多个不同的组合物沉积前体流入沉积室内的基底。 材料粘附到室内部件表面，从而依次形成。 在这种顺序形成之后，反应性气体流入到与多种不同的沉积前体不同的组合物中并且有效地与这种粘附材料反应的室。 在反应气体流动之后，重复这种顺序形成。 考虑进一步的实现。

公开(公告)号：US07271077B2

公开(公告)日：2007-09-18

申请号：US10734999

申请日：2003-12-12

申请人： Eugene Marsh ,  Brian Vaartstra ,  Paul J. Castrovillo ,  Cem Basceri ,  Garo J. Derderian ,  Gurtej S. Sandhu

发明人： Eugene Marsh ,  Brian Vaartstra ,  Paul J. Castrovillo ,  Cem Basceri ,  Garo J. Derderian ,  Gurtej S. Sandhu

IPC分类号： H01L21/36 ,  H01L21/20

CPC分类号： C30B25/14 ,  C23C16/45527 ,  C30B25/02

摘要： An atomic layer deposition method includes positioning a semiconductor substrate within an atomic layer deposition chamber. A first precursor gas is flowed to the substrate within the atomic layer deposition chamber effective to form a first monolayer on the substrate. The first precursor gas flowing comprises a plurality of first precursor gas pulses. The plurality of first precursor gas pulses comprises at least one total period of time between two immediately adjacent first precursor gas pulses when no gas is fed to the chamber. After forming the first monolayer on the substrate, a second precursor gas different in composition from the first is flowed to the substrate within the deposition chamber effective to form a second monolayer on the first monolayer. Other aspects and implementations are contemplated.

摘要翻译： 原子层沉积方法包括将半导体衬底定位在原子层沉积室内。 第一前体气体流到原子层沉积室内的衬底，有效地在衬底上形成第一单层。 第一前体气体流动包括多个第一前体气体脉冲。 多个第一前体气体脉冲包括当没有气体被供给到腔室时在两个紧邻的第一前体气体脉冲之间的至少一个总时间段。 在衬底上形成第一单层之后，组成不同于第一衬底的第二前体气体流入沉积室内的衬底，有效地在第一单层上形成第二单层。 考虑了其他方面和实现。