公开(公告)号：US20050145169A1

公开(公告)日：2005-07-07

申请号：US10630544

申请日：2003-07-29

Applicant: Tongbi Jiang ,  Chad Cobbley ,  John VanNortwick

Inventor： Tongbi Jiang ,  Chad Cobbley ,  John VanNortwick

IPC: B41C1/14 ,  B41N1/24 ,  H05K3/12 ,  B05C11/11

CPC classification number: B41C1/14 ,  B41N1/242 ,  H01L2224/4826 ,  H05K3/1225 ,  Y10S438/945

Abstract: A method and apparatus for improved stencil/screen print quality is disclosed. The stencil or screen assists in application of a printable material onto a substrate, such as an adhesive to a semiconductor die of a semiconductor wafer during a lead-on-chip (LOC) packaging process. In one embodiment, the stencil includes a coating applied to at least one surface of a pattern of the stencil or screen to retard running of the printable material onto the surface. In another embodiment, the stencil or screen includes a second coating applied to at least one other surface of the pattern to promote spreading of the printable material onto the substrate.

Abstract translation: 公开了一种用于改进模板/丝网印刷质量的方法和装置。 在片上（LOC）包装过程中，模板或屏幕有助于将可印刷材料施加到基板上，例如到半导体晶片的半导体管芯的粘合剂。 在一个实施例中，模板包括施加到模板或筛网的图案的至少一个表面上的涂层，以延迟可印刷材料在表面上的运行。 在另一个实施例中，模板或丝网包括施加到图案的至少一个其他表面的第二涂层，以促进可印刷材料在基底上的铺展。

公开(公告)号：US06900080B2

公开(公告)日：2005-05-31

申请号：US10925505

申请日：2004-08-24

Applicant: Tongbi Jiang ,  Farrah J. Storli

Inventor： Tongbi Jiang ,  Farrah J. Storli

IPC: H01L21/56 ,  H01L23/31 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC classification number: H01L23/3128 ,  H01L21/563 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A microelectronic package and method for manufacture. The package can include a support member and a microelectronic substrate positioned at least proximate to the support member. The microelectronic substrate can have a first surface and a second surface facing opposite the first surface, with the first surface having an outer edge and facing toward the support member. At least a portion of the first surface can be spaced apart from an interior surface of the support member to define an intermediate region. At least one conductive coupler is coupled between the microelectronic substrate and the support member. A generally electrically non-conductive material is positioned in the intermediate region with the material contacting the support member and the first surface of the microelectronic substrate and having an outer surface recessed inwardly from the outer edge of the microelectronic substrate.

Abstract translation: 一种微电子封装及其制造方法。 封装可以包括支撑构件和至少邻近支撑构件定位的微电子衬底。 微电子衬底可以具有第一表面和与第一表面相对的第二表面，其中第一表面具有外边缘并面向支撑构件。 第一表面的至少一部分可以与支撑构件的内表面间隔开以限定中间区域。 至少一个导电耦合器耦合在微电子衬底和支撑构件之间。 通常不导电的材料定位在中间区域中，其中材料与微电子衬底的支撑构件和第一表面接触，并且具有从微电子衬底的外边缘向内凹陷的外表面。

公开(公告)号：US06893952B2

公开(公告)日：2005-05-17

申请号：US10358810

申请日：2003-02-05

Applicant: Tongbi Jiang ,  Salman Akram

Inventor： Tongbi Jiang ,  Salman Akram

IPC: H01L21/60 ,  H01L23/485 ,  H05K3/34 ,  H01L21/44

CPC classification number: H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/81136 ,  H01L2224/81801 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/19041 ,  H05K3/3436 ,  H05K2201/0212 ,  H05K2201/10234 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/05611 ,  H01L2924/00014 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655

Abstract: A ball grid array for a flip-chip assembly is disclosed. The ball grid array includes a plurality of bumps bonded between an active surface of a semiconductor die and a top surface of a printed circuit board or any type of substrate carrier. The plurality of balls include at least one bump having a core material and an outer layer. The rigidity of the core material is greater than that of the material of the outer layer. Additionally, the melting temperature of the core material is higher than the material of the outer layer. By this arrangement, the core material with an outer layer provides bumps that are substantially uniform in height. In addition, the balls only procure marks or deformation to the core material during burn-in testing and reflow. Therefore, when bonding the semiconductor device to the substrate, the ball grid array provides sufficient electrical and mechanical connection despite any non-planarity in the active surface of the semiconductor device and the top surface of the substrate, and any differing height in the plurality of balls due to testing the semiconductor device.

Abstract translation: 公开了一种用于倒装芯片组件的球栅阵列。 球栅阵列包括结合在半导体管芯的有源表面和印刷电路板的顶表面之间的多个凸起或任何类型的衬底载体。 多个球包括至少一个具有芯材料和外层的凸块。 芯材的刚性大于外层材料的刚性。 此外，芯材料的熔化温度高于外层的材料。 通过这种布置，具有外层的芯材料提供高度基本均匀的凸块。 此外，在老化测试和回流过程中，球只会对芯材料产生痕迹或变形。 因此，当将半导体器件接合到衬底时，尽管在半导体器件的有源表面和衬底的顶表面中存在任何非平坦性，但球栅阵列提供足够的电和机械连接，并且多个 由于测试了半导体器件。

公开(公告)号：US06891108B2

公开(公告)日：2005-05-10

申请号：US09971985

申请日：2001-10-04

Applicant: Casey Prindiville ,  Tongbi Jiang ,  Bret Street

Inventor： Casey Prindiville ,  Tongbi Jiang ,  Bret Street

IPC: H01L21/56 ,  H01L21/66 ,  H05K1/03

CPC classification number: H01L22/20 ,  H01L21/565 ,  H01L24/97 ,  H01L2224/4824 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  Y10T29/4913 ,  H01L2224/85 ,  H01L2924/00

Abstract: Semiconductor package support elements including cover members attached to one or more reject die sites. Also, methods for making the support elements and for making semiconductor packages using the same. Reject die sites on defective substrates of a support element are covered prior to the encapsulation process using a cover member. The cover member comprises, for example, pressure-sensitive or temperature-activated tape, reject dies, or the like. The support elements and methods of the present invention virtually eliminate bleeding or flashing during encapsulation due to the presence of reject die sites. The support elements and methods of the present invention further ensure that functional dice are not sacrificed by being attached to reject die sites, thereby decreasing manufacturing costs while increasing yield of functional semiconductor packages.

Abstract translation: 半导体封装支撑元件包括附接到一个或多个废弃模具位置的盖构件。 而且，制造支撑元件的方法以及使用该支撑元件制造半导体封装的方法。 在使用盖构件的封装工艺之前，覆盖支撑元件的有缺陷的基底上的模具位置。 盖构件包括例如压敏或温度活化的带，废模或类似物。 本发明的支撑元件和方法由于存在废弃模具位置而实际上消除了在封装期间的渗出或闪烁。 本发明的支撑元件和方法进一步确保功能性骰子不会被附着到废弃模具位置而牺牲，从而降低制造成本，同时提高功能性半导体封装的产量。

公开(公告)号：US06889430B2

公开(公告)日：2005-05-10

申请号：US10020352

申请日：2001-12-12

Applicant: Tongbi Jiang ,  Partrick Tandy

Inventor： Tongbi Jiang ,  Partrick Tandy

IPC: H01L23/31 ,  H01L23/495 ,  H05K3/34

CPC classification number: H01L23/3107 ,  H01L23/4951 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49171 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of selectively adjusting surface tension of a soldermask material. Specifically, a method of selectively adjusting the surface tension of a soldermask material to promote adhesion of a molding compound in a ball grid array package while maintaining a low surface tension on the ball attach area to prevent bridging between the solder balls. Solder balls require a low surface tension soldermask to minimize bridging, while the molding compound requires a high surface tension to provide adequate adhesion to the surface of the soldermask. By exposing selected portions of the soldermask to an activation method, such as ultra-violet radiation, the surface tension of the soldermask can be varied such that different areas of the package exhibit different surface tensions.

Abstract translation: 选择性地调节焊接材料的表面张力的方法。 具体地说，可以选择性地调节焊料材料的表面张力以促进模塑料在球栅阵列封装中的粘附，同时保持球附着区域上的低表面张力以防止焊球之间的桥接。 焊球需要低表面张力焊接掩模以最小化桥接，而模塑料需要高表面张力以提供对焊接表面的足够的粘附。 通过将焊接掩模的选定部分暴露于诸如紫外辐射的激活方法，可以改变焊接掩模的表面张力，使得封装的不同区域表现出不同的表面张力。

公开(公告)号：US06881606B2

公开(公告)日：2005-04-19

申请号：US10391080

申请日：2003-03-18

Applicant: Tongbi Jiang ,  Zhiping Yin ,  Mike Connell

Inventor： Tongbi Jiang ,  Zhiping Yin ,  Mike Connell

IPC: H01L21/56 ,  H01L23/29 ,  H01L23/31 ,  H01L21/50

CPC classification number: H01L23/291 ,  H01L21/565 ,  H01L23/3192 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a semiconductor device having a protective layer for use in packaging the semiconductor device. The apparatus includes a dielectric layer, a first passivation layer formed above the dielectric layer, and a protective layer formed above the first passivation layer, the protective layer adapted to reduce stress defect failures in the semiconductor device when packaged.

Abstract translation: 本发明提供一种具有用于封装半导体器件的保护层的半导体器件。 该装置包括电介质层，形成在电介质层之上的第一钝化层以及形成在第一钝化层之上的保护层，该保护层适于在包装时减少半导体器件中的应力缺陷故障。

公开(公告)号：US20050007142A1

公开(公告)日：2005-01-13

申请号：US10900771

申请日：2004-07-27

Applicant: Chad Cobbley ,  John VanNortwick ,  Bret Street ,  Tongbi Jiang

Inventor： Chad Cobbley ,  John VanNortwick ,  Bret Street ,  Tongbi Jiang

IPC: G01R1/04 ,  G01R31/26

CPC classification number: G01R1/0483 ,  Y10T29/4913 ,  Y10T29/49144

Abstract: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.

Abstract translation: 每个包括集成电路（IC）裸片和相关衬底的倒装芯片半导体组件在封装之前使用在线或原位测试插座或芯片附接站的探针进行电测试。 在通过将集成电路（IC）芯片压在基板上的互连点以进行电连接的环氧树脂固化之前，可以测试使用“湿”快速固化环氧树脂进行芯片附接的那些组件，而使用“干”环氧树脂的那些组件 在测试之前进行治愈。 在任一种情况下，骰子或骰子与基板之间的互连中的任何故障都可以很容易地固定，并且消除了在维修期间使用已知好模具（KGD）返工程序的需要。

公开(公告)号：US06825569B2

公开(公告)日：2004-11-30

申请号：US09258961

申请日：1999-03-01

Applicant: Tongbi Jiang ,  Edward Schrock

Inventor： Tongbi Jiang ,  Edward Schrock

IPC: H01L2348

CPC classification number: H01L23/3107 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/85424 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A BGA package and a method of fabricating the BGA package is provided. The package includes a substrate having a first surface with a pattern of conductors thereon, and an opposing second surface with a die attach area thereon. A first solder mask is formed on the first surface with via openings to ball bonding pads on the conductors. A second solder mask is formed on the second surface with an opening on the die attach area. The opening in the second solder mask permits a die to be placed through the opening and adhesively bonded directly to the substrate. The die can then be wire bonded to the conductors and encapsulated in an encapsulating resin. In addition solder balls can be placed in the via openings and bonded to the ball bonding pads.

Abstract translation: 提供BGA封装和制造BGA封装的方法。 该封装包括具有其上具有导体图案的第一表面的基板和在其上具有管芯附着区域的相对的第二表面。 在第一表面上形成有第一焊接掩模，其中通孔与导体上的焊盘焊接。 在第二表面上形成第二焊料掩模，在管芯附着区域上具有开口。 第二焊接掩模中的开口允许模具通过开口放置并且直接粘合到基板上。 然后可以将管芯引线接合到导体并封装在封装树脂中。 此外，焊球可以放置在通孔开口中并结合到球焊接垫上。

公开(公告)号：US06803657B2

公开(公告)日：2004-10-12

申请号：US09295709

申请日：1999-04-21

Applicant: Tongbi Jiang ,  Syed S. Ahmad

Inventor： Tongbi Jiang ,  Syed S. Ahmad

IPC: H01L2348

CPC classification number: H01L24/12 ,  H01L21/56 ,  H01L23/24 ,  H01L23/4951 ,  H01L24/11 ,  H01L2224/13099 ,  H01L2224/1319 ,  H01L2224/83191 ,  H01L2224/92147 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H05K1/095 ,  H05K3/12 ,  H05K3/305 ,  H05K3/321 ,  H05K2203/1563 ,  H05K2203/159 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A method of forming high definition elements for electrical and electronic devices, substrates, and other components from or including viscous material. The method includes inverting the electrical components after the viscous material is applied and maintaining the inverted orientation until the viscous material dries or cures enough to maintain definition of its perimeter and edge characteristics.

Abstract translation: 从粘性材料形成或包括粘性材料的电气和电子器件，衬底和其它部件的高清晰度元件的方法。 该方法包括在施加粘性材料之后倒置电气部件并保持反向取向，直到粘性材料干燥或固化足够，以保持其周长和边缘特性的定义。

公开(公告)号：US06737299B1

公开(公告)日：2004-05-18

申请号：US09665430

申请日：2000-09-19

Applicant: Tongbi Jiang

Inventor： Tongbi Jiang

IPC: H01L2144

CPC classification number: H01L23/3736 ,  H01L23/36 ,  H01L23/3735 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A thermally conductive adhesive tape and method for its use in packaging integrated circuits fabricated on semiconductor material. The thermally conductive adhesive tape includes a thermally conductive base upon which an adhesive layer is laminated or coated onto at least one side of the thermally conductive base. Thermal energy generated by operating the integrated circuit may be transferred from the integrated circuit via the thermally conductive adhesive tape to a medium to which the semiconductor material is attached. As a result, any excessive heat that may negatively affect the performance of the integrated circuit is dissipated through the medium.

Abstract translation: 一种导热胶带及其用于封装在半导体材料上制造的集成电路的方法。 导热性粘合带包括导热性基材，粘合剂层层叠或涂覆在导热性基材的至少一面上。 通过操作集成电路产生的热能可以从集成电路经由导热胶带转移到附接有半导体材料的介质。 因此，可能会对集成电路的性能产生负面影响的任何过热消散通过介质。