公开(公告)号：US20180182706A1

公开(公告)日：2018-06-28

申请号：US15324646

申请日：2014-08-08

Applicant: Renesas Electronics Corporation

Inventor： Yoshihiro NOMURA

IPC: H01L23/525

CPC classification number: H01L23/5256 ,  H01L21/82 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/0617

Abstract: A semiconductor device includes an insulating film formed to cover an electric fuse (EF1), an insulating film (IL1), an insulating film (IL2), an electric fuse (EF1), an insulating film (IL1), and an insulating film (IL2). The electric fuse (EF1) includes a fuse-blowing portion (FC1), a first pad portion (PD1), and a second pad portion (PD2). The fuse-blowing portion (FC1) is formed between the first pad portion (PD1) and the second pad portion (PD2) in a first direction and is a rectangular shape having a first short side and a second short side along a second direction perpendicular to the first direction. The insulating film (IL1) is formed continuously between the first short side and the second short side to cover the surface of the fuse-blowing portion (FC1). The insulating film (IL2) is formed to planarly surround the insulating film (IL1) and is arranged at an interval from the insulating film (IL1). The stress of the insulating film (IL1) and the insulating film (IL2) is greater than a stress of the insulating film covering the insulating films.

公开(公告)号：US09881916B2

公开(公告)日：2018-01-30

申请号：US15335460

申请日：2016-10-27

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Tatsuya Naito ,  Masahito Otsuki

IPC: H01L29/66 ,  H01L27/06 ,  H01L21/822 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/04 ,  H01L27/088 ,  H01L29/06 ,  H03K17/08 ,  H01L29/423 ,  H01L29/739 ,  H02H3/08 ,  H03K17/12

CPC classification number: H01L27/0635 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/823418 ,  H01L27/04 ,  H01L27/06 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/06 ,  H01L29/0634 ,  H01L29/4236 ,  H01L29/7397 ,  H01L29/78 ,  H01L29/7827 ,  H02H3/08 ,  H03K17/08 ,  H03K17/122 ,  H03K17/127

Abstract: To improve a tradeoff between ON voltage and ON/OFF loss while maintaining short-circuit tolerance, provided is a semiconductor device including an IGBT element; a super junction transistor element connected in parallel with the IGBT element; and a limiting section that limits a voltage applied to a gate terminal of the IGBT element more than a voltage applied to a gate terminal of the super junction transistor element.

公开(公告)号：US20170236856A1

公开(公告)日：2017-08-17

申请号：US15501506

申请日：2015-07-30

Applicant: Sharp Kabushiki Kaisha

Inventor： Kazuhide TOMIYASU ,  Tadayoshi MIYAMOTO

IPC: H01L27/146 ,  H04N5/32 ,  G01T1/20

CPC classification number: H01L27/14603 ,  G01T1/2018 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/1225 ,  H01L27/144 ,  H01L27/146 ,  H01L27/14616 ,  H01L27/14636 ,  H01L27/14663 ,  H01L27/14689 ,  H01L29/78693 ,  H04N5/32

Abstract: It is an object of the invention to secure a large area of a photodiode and suppress operation property variation and malfunction in an imaging panel and an X-ray imaging device. An imaging panel (10) includes a substrate (40), a TFT (14), an interlayer insulating film (44), a metal layer (45), and a photodiode (15). A data line (12) and the photodiode (15) face each other in a thickness direction of the substrate. The interlayer insulating film (44), which is disposed between the TFT (14) and the photodiode (15), is an SOG film or a photosensitive resin film.

公开(公告)号：US09735112B2

公开(公告)日：2017-08-15

申请号：US14593642

申请日：2015-01-09

Applicant: Fairchild Semiconductor Corporation

Inventor： John Constantino ,  Timwah Luk ,  Ahmad Ashrafzadeh ,  Robert L. Krause ,  Etan Shacham ,  Maria Clemens Ypil Quinones ,  Janusz Bryzek ,  Chung-Lin Wu

IPC: H01L23/538 ,  H01L27/06 ,  H01L49/02 ,  H01L23/495 ,  H01L23/66

CPC classification number: H01L23/538 ,  H01L23/49531 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/49589 ,  H01L23/66 ,  H01L27/06 ,  H01L28/40 ,  H01L2224/0603 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2924/13055 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: In some general aspects, an apparatus may include a first semiconductor die, a second semiconductor die, and a capacitive isolation circuit being coupled to the first semiconductor die and the second semiconductor die. The capacitive isolation circuit may be disposed outside of the first semiconductor die and the second semiconductor die. The first semiconductor die, the second semiconductor die, and the capacitive circuit may be included in a molding of a semiconductor package.

公开(公告)号：US20170194164A1

公开(公告)日：2017-07-06

申请号：US15462583

申请日：2017-03-17

Applicant: Renesas Electronics Corporation

Inventor： Takuo FUNAYA ,  Takayuki IGARASHI

IPC: H01L21/3205 ,  H01L49/02 ,  H01L21/02 ,  H01L21/66 ,  H01L23/00 ,  H01L23/522 ,  H01L27/06

CPC classification number: H01L21/3205 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02271 ,  H01L22/14 ,  H01L22/32 ,  H01L23/49575 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/5283 ,  H01L24/03 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L27/06 ,  H01L27/0617 ,  H01L27/0688 ,  H01L28/10 ,  H01L2223/6655 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01015

Abstract: A method of manufacturing a semiconductor device including: (a) forming a first insulation film on a semiconductor substrate; (b) forming a first coil on the first insulation film; (c) forming a second insulation film on the first insulation film so as to cover the first coil; (d) forming a first pad on the second insulation film at a position not overlapped with the first coil in a planar view; (e) forming a laminated insulation film on the second insulation film, the laminated insulation film having a first opening from which the first pad is exposed; and (f) forming a second coil and a first wiring on the laminated insulation film, wherein the second coil is disposed above the first coil, the first coil and the second coil are not connected by a conductor but magnetically coupled to each other, the first wiring is formed from an upper portion of the first pad to an upper portion of the laminated insulation film and is electrically connected to the first pad, and the laminated insulation film includes a silicon oxide film, a silicon nitride film on the silicon oxide film, and a resin film on the silicon nitride film.

公开(公告)号：US20170141099A1

公开(公告)日：2017-05-18

申请号：US15420533

申请日：2017-01-31

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Satoshi UNO ,  Hiroshi KAWAGUCHI

IPC: H01L27/02 ,  H01L27/08 ,  H01L29/861

CPC classification number: H01L27/0255 ,  H01L21/822 ,  H01L21/8222 ,  H01L27/0207 ,  H01L27/0248 ,  H01L27/0292 ,  H01L27/04 ,  H01L27/06 ,  H01L27/0814 ,  H01L29/20 ,  H01L29/861 ,  H01L29/8613

Abstract: Connection patterns of plural diodes include a first series connection pattern and a second series connection pattern. The first series connection pattern extends from an input terminal in the X direction. The second series connection pattern has a portion through which a current flows to approach the input terminal. The first series connection pattern includes a first diode, which is the first diode counted from the input terminal. The second series connection pattern includes a second diode, which is the last diode counted from the input terminal. The second diode is disposed separately from the first diode with some distance therebetween in the Y direction. An N-type region of the first diode and a P-type region of the second diode directly oppose each other as viewed in a planar direction.

公开(公告)号：US20170062425A1

公开(公告)日：2017-03-02

申请号：US15064062

申请日：2016-03-08

Applicant: Verisiti, Inc.

Inventor： William Eli Thacker

IPC: H01L27/092 ,  H01L23/00 ,  H03K19/20

CPC classification number: H01L27/0922 ,  H01L21/82 ,  H01L23/573 ,  H01L27/0203 ,  H01L27/06 ,  H01L28/24 ,  H01L2924/0002 ,  H03K19/20 ,  H01L2924/00

Abstract: It is desirable to design and manufacture electronic chips that are resistant to modern reverse engineering techniques. Disclosed is a method and device that allows for the design of chips that are difficult to reverse engineer using modern teardown techniques. The disclosed device uses devices having the same geometry but different voltage levels to create different logic devices. Alternatively, the disclosed uses devices having different geometries and the same operating characteristics. Also disclosed is a method of designing a chip using these devices.

Abstract translation: 希望设计和制造耐现代逆向工程技术的电子芯片。 公开了允许使用现代拆卸技术难以逆向工程的芯片的设计的方法和装置。 所公开的设备使用具有相同几何但具有不同电压电平的设备来创建不同的逻辑设备。 或者，所公开的使用具有不同几何形状和相同操作特性的装置。 还公开了使用这些装置设计芯片的方法。

公开(公告)号：US20170047320A1

公开(公告)日：2017-02-16

申请号：US15335460

申请日：2016-10-27

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Tatsuya NAITO ,  Masahito OTSUKI

IPC: H01L27/06 ,  H02H3/08 ,  H01L29/78 ,  H01L29/423 ,  H01L29/739 ,  H01L29/06

CPC classification number: H01L27/0635 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/823418 ,  H01L27/04 ,  H01L27/06 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/06 ,  H01L29/0634 ,  H01L29/4236 ,  H01L29/7397 ,  H01L29/78 ,  H01L29/7827 ,  H02H3/08 ,  H03K17/08 ,  H03K17/122 ,  H03K17/127

Abstract: To improve a tradeoff between ON voltage and ON/OFF loss while maintaining short-circuit tolerance, provided is a semiconductor device including an IGBT element; a super junction transistor element connected in parallel with the IGBT element; and a limiting section that limits a voltage applied to a gate terminal of the IGBT element more than a voltage applied to a gate terminal of the super junction transistor element.

Abstract translation: 为了在保持短路公差的同时提高ON电压和ON / OFF损耗之间的折衷，提供了包括IGBT元件的半导体器件; 与IGBT元件并联连接的超结晶体管元件; 以及限制施加到IGBT元件的栅极端子的电压，而不是施加到超结晶体管元件的栅极端子的电压。

公开(公告)号：US20170018606A1

公开(公告)日：2017-01-19

申请号：US15278816

申请日：2016-09-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： KEVIN K. CHAN ,  BAHMAN HEKMATSHOARTABARI ,  TAK H. NING

IPC: H01L29/06 ,  H01L29/167 ,  H01L29/66 ,  H01L29/735

CPC classification number: H01L29/0638 ,  H01L27/06 ,  H01L27/0623 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/167 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/66234 ,  H01L29/6625 ,  H01L29/66272 ,  H01L29/66287 ,  H01L29/732 ,  H01L29/735 ,  H01L29/7398

Abstract: A method for forming a bipolar junction transistor includes forming a collector intrinsic region, an emitter intrinsic region and an intrinsic base region between the collector intrinsic region and the emitter intrinsic region. A collector extrinsic contact region is formed in direct contact with the collector intrinsic region; an emitter extrinsic contact region is formed on the emitter intrinsic region and a base extrinsic contact region is formed in direct contact with the intrinsic base region. Carbon is introduced into at least one of the collector extrinsic contact region, the emitter extrinsic contact region and the base extrinsic contact region to suppress diffusion of dopants into the junction region.

Abstract translation: 用于形成双极结型晶体管的方法包括在集电极本征区域和发射极本征区域之间形成集电极本征区域，发射极本征区域和本征基极区域。 集电体外部接触区域与集电极本征区域直接接触形成; 在发射极本征区域上形成发射极外部接触区域，并且形成与本征基极区域直接接触的基本非本征接触区域。 将碳引入到集电体外部本征接触区域，发射极非本征接触区域和基本非本征接触区域中的至少一个中，以抑制掺杂剂扩散到接合区域中。

公开(公告)号：US20170017416A1

公开(公告)日：2017-01-19

申请号：US14829644

申请日：2015-08-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： ZHIBIAO ZHOU ,  Shao-Hui Wu ,  Chi-Fa Ku ,  Chen-Bin Lin

IPC: G06F3/06 ,  G11C11/4076

CPC classification number: G06F1/3293 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3287 ,  G11C5/141 ,  G11C7/1006 ,  G11C16/00 ,  G11C2211/4016 ,  H01L27/06 ,  H01L27/07 ,  H01L27/108

Abstract: A semiconductor device includes a main processor, a normally-off processor, and at least one oxide semiconductor random access memory (RAM). The normally-off processor includes at least one oxide semiconductor transistor. The main processor is connected to the normally-off processor, and a clock rate of the main processor is higher than a clock rate of the normally-off processor. The oxide semiconductor RAM is connected to the normally-off processor. An operating method of the semiconductor includes backing up data from the main processor to the normally-off process and/or the oxide semiconductor RAM.

Abstract translation: 半导体器件包括主处理器，常关处理器和至少一个氧化物半导体随机存取存储器（RAM）。 常关处理器包括至少一个氧化物半导体晶体管。 主处理器连接到常关处理器，并且主处理器的时钟速率高于常关处理器的时钟速率。 氧化物半导体RAM连接到常关处理器。 半导体的操作方法包括将数据从主处理器备份到常关处理和/或氧化物半导体RAM。