公开(公告)号：US20060068513A1

公开(公告)日：2006-03-30

申请号：US11234758

申请日：2005-09-23

申请人： Hiroshi Funakubo ,  Yoshihisa Honda ,  Nataliya Nabatova-Gabain ,  Asuka Terai

发明人： Hiroshi Funakubo ,  Yoshihisa Honda ,  Nataliya Nabatova-Gabain ,  Asuka Terai

IPC分类号： H01L21/66 ,  G01R31/26

CPC分类号： G01N21/211 ,  C23C16/52 ,  G01B11/0641 ,  H01L21/02197 ,  H01L21/31691 ,  H01L28/56

摘要： Among a plurality of parameters concerning a film forming condition, different parameter values are set for one parameter and the same predetermined values are set for other parameters to manufacture two pieces of film structures including a high-dielectric constant film or ferroelectric film formed on a substrate. The film characteristics of the respective film structures are analyzed by a spectroscopic ellipsometer, a film structure in which the ratio of the presence of an accompanying dielectric film is smaller, is determined to be good by comparing the analysis results, and a parameter value set for the manufacture of the good film structure is determined. Then similar processing is performed, to specify an optimal parameter value for one parameter, and similar processing is also performed for other parameters to specify an optimal parameter value for the other parameters.

公开(公告)号：US07012306B2

公开(公告)日：2006-03-14

申请号：US10819306

申请日：2004-04-07

申请人： Mårten Armgarth ,  Miaioxiang Chen ,  David A. Nilsson ,  Rolf M. Berggren ,  Thomas Kugler ,  Tommi M. Remonen ,  Robert Forchheimer

发明人： Mårten Armgarth ,  Miaioxiang Chen ,  David A. Nilsson ,  Rolf M. Berggren ,  Thomas Kugler ,  Tommi M. Remonen ,  Robert Forchheimer

IPC分类号： H01L23/62

CPC分类号： H01L51/0508 ,  B82Y10/00 ,  C09K9/02 ,  G02F1/163 ,  G02F2001/1635 ,  G02F2202/022 ,  G11C13/0009 ,  G11C13/0014 ,  G11C13/0016 ,  G11C2213/15 ,  H01L21/31604 ,  H01L27/283 ,  H01L28/56 ,  H01L51/0037 ,  H01L51/0097 ,  H01L51/052 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrochemical transistor device is provided, comprising a source contact, a drain contact, at least one gate electrode, an electrochemically active element arranged between, and in direct electrical contact with, the source and drain contacts, which electrochemically active element comprises a transistor channel and is of a material comprising an organic material having the ability of electrochemically altering its conductivity through change of redox state thereof, and a solidified electrolyte in direct electrical contact with the electrochemically active element and said at least one gate electrode and interposed between them in such a way that electron flow between the electrochemically active element and said gate electrode(s) is prevented. In the device, flow of electrons between source contact and drain contact is controllable by means of a voltage applied to said gate electrode(s). Also provided are circuits incorporating such electrochemical transistor devices and processes for the production of such devices.

摘要翻译： 提供了一种电化学晶体管器件，其包括源极接触，漏极接触，至少一个栅电极，布置在源极和漏极接触之间并与源极和漏极触点直接电接触的电化学有源元件，该电化学有源元件包括晶体管沟道 并且是包含具有通过氧化还原状态的电化学改变其导电性的能力的有机材料的材料，以及与电化学活性元件和所述至少一个栅电极直接电接触并固定在它们之间的固化电解质， 防止电化学活性元件和所述栅电极之间的电子流动的方式。 在器件中，通过施加到所述栅电极的电压来控制源极接触和漏极接触之间的电子流。 还提供了结合这种电化学晶体管器件的电路和用于生产这种器件的工艺。

公开(公告)号：US07002788B2

公开(公告)日：2006-02-21

申请号：US11032150

申请日：2005-01-11

申请人： Yong-kuk Jeong ,  Jung-Hyoung Lee ,  Seok-Jun Won ,  Dae-Jin Kwon ,  Weon-Hong Kim ,  Min-woo Song

发明人： Yong-kuk Jeong ,  Jung-Hyoung Lee ,  Seok-Jun Won ,  Dae-Jin Kwon ,  Weon-Hong Kim ,  Min-woo Song

IPC分类号： H01G4/06

CPC分类号： H01L21/02172 ,  H01G4/10 ,  H01G4/20 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/3141 ,  H01L21/31645 ,  H01L27/0805 ,  H01L28/56 ,  H01L28/65

摘要： In a capacitor, and a method of fabricating the same, the capacitor includes a lower electrode, a dielectric layer on the lower electrode, and an upper electrode on the dielectric layer, wherein the dielectric layer includes a lower dielectric region contacting the lower electrode, an upper dielectric region contacting the upper electrode, and at least one middle dielectric region between the lower dielectric region and the upper dielectric region, the at least one middle dielectric region having a less crystalline region than both the lower dielectric region and the upper dielectric region.

公开(公告)号：US07002202B2

公开(公告)日：2006-02-21

申请号：US10688823

申请日：2003-10-17

申请人： Sam Yang ,  Vishnu K. Agarwal

发明人： Sam Yang ,  Vishnu K. Agarwal

IPC分类号： H01L27/108

CPC分类号： H01L28/56 ,  H01L27/10852 ,  H01L28/75

摘要： Capacitor structures for use in integrated circuits and methods of their manufacture. The capacitor structures include a bottom electrode, a top electrode and a dielectric layer interposed between the bottom electrode and the top electrode. The capacitor structures further include a metal oxynitride barrier layer interposed between the dielectric layer and at least one of the bottom and top electrodes. Each metal oxynitride barrier layer acts to reduce undesirable oxidation of its associated electrode. Each metal oxynitride barrier layer can further aid in the repairing of oxygen vacancies in a metal oxide dielectric. The capacitors are suited for use as memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

公开(公告)号：US20060035390A1

公开(公告)日：2006-02-16

申请号：US11249883

申请日：2005-10-12

申请人： Tingkai Li ,  Sheng Hsu

发明人： Tingkai Li ,  Sheng Hsu

IPC分类号： H01L21/469

CPC分类号： H01L21/28273 ,  C23C16/0272 ,  C23C16/40 ,  C23C16/56 ,  H01L21/28194 ,  H01L21/28291 ,  H01L21/31691 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517

摘要： A method of forming a ferroelectric thin film on a high-k layer includes preparing a silicon substrate; forming a high-k layer on the substrate; depositing a seed layer of ferroelectric material at a relatively high temperature on the high-k layer; depositing a top layer of ferroelectric material on the seed layer at a relatively low temperature; and annealing the substrate, the high-k layer and the ferroelectric layers to form a ferroelectric thin film.

公开(公告)号：US20060022245A1

公开(公告)日：2006-02-02

申请号：US11187489

申请日：2005-07-22

申请人： Yong-kuk Jeong ,  Seok-jun Won ,  Dae-jin Kwon ,  Min-woo Song ,  Weon-hong Kim

发明人： Yong-kuk Jeong ,  Seok-jun Won ,  Dae-jin Kwon ,  Min-woo Song ,  Weon-hong Kim

IPC分类号： H01L29/94

CPC分类号： H01L21/022 ,  H01L21/02172 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/3143 ,  H01L21/31604 ,  H01L21/31616 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31691 ,  H01L27/0805 ,  H01L28/56

摘要： An analog capacitor capable of reducing the influence of an applied voltage on a capacitance and a method of manufacturing the analog capacitor are provided. The analog capacitor includes a lower electrode which is formed on a substrate, a multi-layered dielectric layer which includes at least one oxide layer and at least one oxynitride layer which are formed of a material selected from the group consisting of Hf, Al, Zr, La, Ba, Sr, Ti, Pb, Bi and a combination thereof and is formed on the lower electrode, and an upper electrode which is formed on the multi-layered dielectric layer.

摘要翻译： 提供了能够减小施加电压对电容的影响的模拟电容器和制造模拟电容器的方法。 模拟电容器包括形成在基板上的下电极，包括至少一个氧化物层和至少一个氧氮化物层的多层电介质层，所述至少一个氧氮化物层由选自Hf，Al，Zr La，Ba，Sr，Ti，Pb，Bi及其组合形成在下电极上，形成在多层电介质层上的上电极。

公开(公告)号：US20050280104A1

公开(公告)日：2005-12-22

申请号：US10870616

申请日：2004-06-17

申请人： Hong-Jyh Li

发明人： Hong-Jyh Li

IPC分类号： H01L21/02 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/51 ,  H01L29/76

CPC分类号： H01L21/823842 ,  H01L21/28088 ,  H01L21/28097 ,  H01L21/823857 ,  H01L27/092 ,  H01L28/56 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/513 ,  H01L29/517

摘要： A CMOS device with transistors having different gate dielectric materials and a method of manufacture thereof. A CMOS device is formed on a workpiece having a first region and a second region. A first gate dielectric material is deposited over the second region. A first gate material is deposited over the first gate dielectric material. A second gate dielectric material comprising a different material than the first gate dielectric material is deposited over the first region of the workpiece. A second gate material is deposited over the second gate dielectric material. The first gate material, the first gate dielectric material, the second gate material, and the second gate dielectric material are then patterned to form a CMOS device having a symmetric Vt for the PMOS and NMOS FETs.

摘要翻译： 具有不同栅介电材料的晶体管的CMOS器件及其制造方法。 在具有第一区域和第二区域的工件上形成CMOS器件。 在第二区域上沉积第一栅极电介质材料。 第一栅极材料沉积在第一栅极电介质材料上。 包括与第一栅极电介质材料不同的材料的第二栅极电介质材料沉积在工件的第一区域上。 第二栅极材料沉积在第二栅极电介质材料上。 然后对第一栅极材料，第一栅极电介质材料，第二栅极材料和第二栅极介电材料进行构图以形成具有用于PMOS和NMOS FET的对称V IN的CMOS器件。

公开(公告)号：US20050258510A1

公开(公告)日：2005-11-24

申请号：US11125654

申请日：2005-05-10

申请人： Martin Gutsche ,  Harald Seidl

发明人： Martin Gutsche ,  Harald Seidl

IPC分类号： H01L21/02 ,  H01L21/316 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/08 ,  H01L29/76

CPC分类号： H01L28/56 ,  H01L21/022 ,  H01L21/31604 ,  H01L21/31608 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645

摘要： The present invention provides a method for fabricating a capacitive element (100), a substrate (101) being provided as a first electrode layer of the capacitive element (100), the substrate (101) provided as an electrode layer is conditioned, a dielectric layer (102) is deposited on the conditioned substrate (101) and a second electrode layer (104) is applied on the layer stack produced, the layer stack being modified by a heat treatment in such a way that the dielectric layer (102) deposited on the conditioned substrate (101) forms a dielectric mixed layer (105) with a reaction layer (103) deposited on the dielectric layer (102), which dielectric mixed layer has an increased dielectric constant (k) or an increased thermal stability.

摘要翻译： 本发明提供一种电容元件（100）的制造方法，设置有作为电容元件（100）的第一电极层的基板（101），将作为电极层设置的基板（101）进行调理， 层（102）沉积在经调理的基底（101）上，并且第二电极层（104）被施加在所产生的层叠层上，通过热处理改变层堆叠，使得介电层（102）沉积 在调理衬底（101）上形成电介质混合层（105），其上沉积有介电层（102）上的反应层（103），该电介质混合层具有增加的介电常数（k）或增加的热稳定性。

公开(公告)号：US06958900B2

公开(公告)日：2005-10-25

申请号：US10375923

申请日：2003-02-26

申请人： Yukio Sakashita

发明人： Yukio Sakashita

IPC分类号： C30B25/18 ,  C30B29/32 ,  H01L21/02 ,  H01L21/316 ,  H01G4/228

CPC分类号： H01L28/56 ,  C30B25/18 ,  C30B29/32 ,  H01L21/31691 ,  H01L28/65 ,  Y10T428/12493 ,  Y10T428/12535

摘要： A multi-layered unit according to the present invention includes a support substrate formed of fused quartz, an electrode layer formed on the support substrate and formed of a conductive material, a buffer layer formed on the electrode layer and formed of a dielectric material containing a bismuth layer structured compound having a composition represented by Bi4Ti3O12 and having an excellent orientation characteristic so that the bismuth layer structured compound is oriented in the c axis direction, and a dielectric layer formed on the buffer layer and formed of a dielectric material containing a bismuth layer structured compound having a composition represented by SrBi4Ti4O15 and having an excellent orientation characteristic so that the bismuth layer structured compound is oriented in the c axis direction. Since the thus constituted multi-layered unit includes the dielectric layer containing the bismuth layer structured compound oriented in the c axis direction, in the case of, for example, providing an upper electrode on the dielectric layer to form a thin film capacitor and applying a voltage between the electrode layer and the upper electrode, the direction of the electric field substantially coincides with the c axis of the bismuth layer structured compound contained in the dielectric layer. As a result, since the ferroelectric property of the bismuth layer structured compound contained in the dielectric layer can be suppressed and the paraelectric property thereof can be fully exhibited, it is possible to fabricate a thin film capacitor having a small size, large capacitance and an excellent dielectric characteristic.

摘要翻译： 根据本发明的多层单元包括由熔融石英形成的支撑基板，形成在支撑基板上并由导电材料形成的电极层，形成在电极层上并由介电材料形成的缓冲层，该介电材料包含 具有由Bi 4 Ti 3 O 12 12表示的组成的铋层结构化合物，并且具有优异的取向特性，使得铋层结构化合物为 在c轴方向上取向，并且形成在缓冲层上并由包含具有由SrBi 4 Ti 4 Si表示的组成的铋层结构化合物的电介质材料形成的电介质层 并且具有优异的取向特性，使得铋层结构化合物在c轴方向上取向。 由于如此构成的多层单元包括在c轴方向上包含铋层结构化合物的电介质层，所以在例如在电介质层上设置上电极以形成薄膜电容器并施加 电极层与上部电极之间的电压，电场方向基本上与包含在电介质层中的铋层结构化合物的c轴重合。 结果，由于可以抑制包含在电介质层中的铋层结构化合物的铁电性能并且可以充分发挥其顺电特性，所以可以制造具有小尺寸，大电容的薄膜电容器和 优良的介电特性。

公开(公告)号：US20050233476A1

公开(公告)日：2005-10-20

申请号：US11081815

申请日：2005-03-17

申请人： Toshitaka Tatsunari

发明人： Toshitaka Tatsunari

IPC分类号： H01L27/04 ,  H01L21/00 ,  H01L21/02 ,  H01L21/316 ,  H01L21/822 ,  H01L21/8246 ,  H01L27/105 ,  H01L29/76 ,  H01L29/78 ,  H01L29/94

CPC分类号： H01L28/56 ,  H01L29/78391

摘要： A method for fabricating a ferroelectric capacitive element of this invention includes the steps of forming a lower electrode made of a first conductive film on a substrate; forming a first ferroelectric film including bismuth in a first concentration on the lower electrode; forming a second ferroelectric film including bismuth in a second concentration on the first ferroelectric film; performing annealing after forming the first ferroelectric film and the second ferroelectric film; and forming an upper electrode made of a second conductive film on the second ferroelectric film after the annealing. The first conductive film is a metal film more easily etched than a platinum film, and the second ferroelectric film is formed in such a manner that the second concentration is lower than the first concentration before the annealing.

摘要翻译： 本发明的铁电电容元件的制造方法包括在基板上形成由第一导电膜构成的下电极的工序; 在下电极上形成包含第一浓度的铋的第一铁电体膜; 在所述第一强电介质膜上形成包含第二浓度的铋的第二铁电体膜; 在形成第一铁电体膜和第二铁电体膜之后进行退火; 以及在退火后在第二铁电体膜上形成由第二导电膜制成的上电极。 第一导电膜是比铂膜更容易蚀刻的金属膜，并且第二强电介质膜以使得第二浓度低于退火前的第一浓度的方式形成。