公开(公告)号：US09831113B2

公开(公告)日：2017-11-28

申请号：US14184191

申请日：2014-02-19

Applicant: Cypress Semiconductor Corporation

Inventor： Fumihiko Inoue ,  Yukio Hayakawa

IPC: H01L21/70 ,  H01L21/762 ,  H01L21/308

CPC classification number: H01L21/76224 ,  H01L21/3086

Abstract: A method of manufacturing a semiconductor device includes forming a silicon nitride film having an opening portion on a semiconductor substrate, forming a silicon oxide film on the silicon nitride film and on a side face of the opening portion, performing an etching treatment to the silicon oxide film so that a sidewall is formed on the side face of the opening portion, forming a trench on the semiconductor substrate with use of the sidewall and the silicon nitride film as a mask, and forming an insulating layer in the trench. The step of forming the silicon oxide film includes oxidizing the silicon nitride film with a plasma oxidation method or a radical oxidation method.

公开(公告)号：US09825126B2

公开(公告)日：2017-11-21

申请号：US15502094

申请日：2015-09-07

Applicant: Mitsubishi Electric Corporation

Inventor： Hideyuki Hatta ,  Naruhisa Miura

IPC: H01L21/70 ,  H01L29/66 ,  H01L29/06 ,  H01L29/16 ,  H01L29/10 ,  H01L29/78 ,  H01L21/04 ,  H01L27/07

CPC classification number: H01L29/063 ,  H01L21/0465 ,  H01L27/0738 ,  H01L27/075 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/1095 ,  H01L29/12 ,  H01L29/1608 ,  H01L29/42376 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/7806 ,  H01L29/7813

Abstract: A source region of a MOSFET includes a source contact region connected to a source electrode, a source extension region adjacent to a channel region of a well region, and a source resistance control region provided between the source extension region and the source contact region. The source resistance control region includes a low concentration source resistance control region which has an impurity concentration lower than that of the source contact region or the source extension region and a high concentration source resistance control region which is formed between the well region and the low concentration source resistance control region and has an impurity concentration higher than that of the low concentration source resistance control region.

公开(公告)号：US20170323826A1

公开(公告)日：2017-11-09

申请号：US15476648

申请日：2017-03-31

Applicant: Twisden Ltd.

Inventor： Loke Chew Low ,  Linhui Yuan

IPC: H01L21/768 ,  H01L23/367 ,  H01L23/13 ,  H01L23/00 ,  H01L21/70

Abstract: An integrated circuit packaging is described, including a plurality of electrical circuits developed using a first patterned conductive layer on a base, wherein an electrical circuit is formed by using a masking material, and an interconnection is developed between the electrical circuits, where the interconnection is disposed on at least one side of the first patterned conductive layer and masking material, in which the interconnection is enclosed with a second masking material to form the integrated circuit packaging.

公开(公告)号：US09793337B2

公开(公告)日：2017-10-17

申请号：US15167783

申请日：2016-05-27

Applicant: MediaTek Inc.

Inventor： Yuan-Fu Chung ,  Chu-Wei Hu ,  Yuan-Hung Chung

IPC: H01L21/70 ,  H01L49/02 ,  H01L21/265 ,  H01L21/268 ,  H01L21/28 ,  H01L21/324 ,  H01L27/06 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/49 ,  H01L21/02 ,  H01L21/266 ,  H01L29/167 ,  H01L21/3215 ,  H01L27/02

CPC classification number: H01L28/20 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/268 ,  H01L21/28035 ,  H01L21/32155 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/8234 ,  H01L21/823437 ,  H01L27/0207 ,  H01L27/0629 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/167 ,  H01L29/4916

Abstract: An integrated circuit includes a first polysilicon region having a first grain size formed on a substrate. The integrated circuit also includes a second polysilicon region, having a second grain size different from the first grain size, formed on the substrate. The first polysilicon region is doped with a first dopant of a first conductive type and a second dopant selected from elements of group IIIA and group IVA which has an atomic weight heavier than that of silicon.

公开(公告)号：US09761684B2

公开(公告)日：2017-09-12

申请号：US15251690

申请日：2016-08-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ju-Li Huang ,  Chao-Cheng Chen ,  Calvin Chiang ,  Ming-Chia Tai ,  Ming-Hsi Yeh

IPC: H01L21/70 ,  H01L29/49 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/51 ,  H01L21/28 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0886 ,  H01L27/092 ,  H01L29/517 ,  H01L29/66545

Abstract: A semiconductor device having metal gates and methods of forming the same are disclosed. The semiconductor device includes a substrate and a gate structure over the substrate. The gate structure includes a gate dielectric layer over the substrate, a barrier layer over the gate dielectric layer, an oxide layer over the barrier layer, and a work function metal layer over the oxide layer.

公开(公告)号：US09741814B2

公开(公告)日：2017-08-22

申请号：US15080657

申请日：2016-03-25

Applicant: Sony Corporation

Inventor： Koichi Matsumoto

IPC: H01L21/70 ,  H01L29/49 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092 ,  H01L29/423 ,  H01L29/417

CPC classification number: H01L27/0924 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28097 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823864 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/42356 ,  H01L29/42376 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/4983 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656

Abstract: A semiconductor device including: a first conductivity type transistor and a second conductivity type transistor, wherein each of the first conductivity type transistor and the second conductivity type includes agate insulating film formed on a base, a metal gate electrode formed on the gate insulating film, and side wall spacers formed at side walls of the metal gate electrode, wherein the gate insulating film is made of a high dielectric constant material, and wherein offset spacers are formed between the side walls of the metal gate electrode and the inner walls of the side wall spacers in any one of the first conductivity type transistor and the second conductivity type transistor, or offset spacers having different thicknesses are formed in the first conductivity type transistor and the second conductivity type transistor.

公开(公告)号：US09741723B2

公开(公告)日：2017-08-22

申请号：US14852852

申请日：2015-09-14

Applicant: Micron Technology, Inc.

Inventor： Tsuyoshi Tomoyama

IPC: H01L21/70 ,  H01L21/76 ,  H01L27/108

CPC classification number: H01L27/10897 ,  H01L21/762 ,  H01L27/10814

Abstract: A semiconductor device is provided, which prevents a case where the widths of word lines become uneven because of a stress developing at the border between a memory cell area and a peripheral circuit area. The semiconductor device 1 has a semiconductor substrate 2 on which a memory cell area MC defined by a peripheral isolation region 3c. The memory cell area MC has multiple cell active regions k defined by multiple cell isolation regions 3a, 3b. Guard active regions GLa, GLb made of the semiconductor substrate are disposed in the border between the memory cell area MC and the peripheral isolation region 3c to separate the memory cell isolation regions 3a, 3b from the peripheral isolation region 3c.

公开(公告)号：US09741719B2

公开(公告)日：2017-08-22

申请号：US14995483

申请日：2016-01-14

Applicant: Tela Innovations, Inc.

Inventor： Michael C. Smayling ,  Scott T. Becker

IPC: H01L21/70 ,  H01L27/092 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  G06F17/50 ,  H01L27/105 ,  H01L23/528 ,  H01L27/02 ,  G03F1/00

CPC classification number: H01L27/092 ,  G03F1/14 ,  G06F17/5077 ,  H01L21/28518 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/823828 ,  H01L21/823871 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/105 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes a gate electrode level region that includes a plurality of linear-shaped conductive structures. Each of the plurality of linear-shaped conductive structures is defined to extend lengthwise in a first direction. Some of the plurality of linear-shaped conductive structures form one or more gate electrodes of corresponding transistor devices. A local interconnect conductive structure is formed between two of the plurality of linear-shaped conductive structures so as to extend in the first direction along the two of the plurality of linear-shaped conductive structures.

公开(公告)号：US09741715B2

公开(公告)日：2017-08-22

申请号：US15179992

申请日：2016-06-11

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Balasubramanian Pranatharthiharan ,  Hui Zang

IPC: H01L21/70 ,  H01L27/088 ,  H01L27/11 ,  H01L29/16 ,  H01L29/06 ,  H01L21/304 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L27/1104 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/02642 ,  H01L21/3043 ,  H01L21/324 ,  H01L21/76 ,  H01L21/76224 ,  H01L21/8221 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/1116 ,  H01L28/00 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a set of fin structures having a set of fin ends at a respective vertical surface of a fin structure and is separated by a set of trenches from other fin structures. Each of the fin structures has a top surface which is higher than a top surface of a dielectric material in the set of trenches. A set of dielectric blocks is disposed at the set of fin ends, the dielectric blocks having a top surface level with or above the top surfaces of the fin structures which inhibit excessive epitaxial growth at the fin ends.

公开(公告)号：US09741620B2

公开(公告)日：2017-08-22

申请号：US14749529

申请日：2015-06-24

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Guilian Gao ,  Liang Wang ,  Hong Shen ,  Arkalgud R. Sitaram

IPC: H01L21/00 ,  H01L21/70 ,  H01L21/82 ,  H01L21/56 ,  H01L23/00 ,  H01L21/48 ,  H01L23/538 ,  H01L23/31

CPC classification number: H01L21/82 ,  H01L21/486 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/96 ,  H01L24/97 ,  H01L24/98 ,  H01L2224/04105 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/3511 ,  H01L2924/3512

Abstract: A device and method of forming the device that includes cavities formed in a substrate of a substrate device, the substrate device also including conductive vias formed in the substrate. Chip devices, wafers, and other substrate devices can be mounted to the substrate device. Encapsulation layers and materials may be formed over the substrate device in order to fill the cavities.