公开(公告)号：US20170117052A1

公开(公告)日：2017-04-27

申请号：US15401858

申请日：2017-01-09

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Jin-Ki KIM ,  Peter B. GILLINGHAM

IPC: G11C16/30 ,  G11C16/14 ,  G11C16/26

CPC classification number: G11C16/30 ,  G11C5/14 ,  G11C5/143 ,  G11C5/145 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26

Abstract: A memory device includes core memory such as flash memory for storing data. The memory device includes a first power input to receive a first voltage used to power the flash memory. Additionally, the memory device includes a second power input to receive a second voltage.The memory device includes power management circuitry configured to receive the second voltage and derive one or more internal voltages. The power management circuitry supplies or conveys the internal voltages to the flash memory. The different internal voltages generated by the power management circuitry (e.g., voltage converter circuit) and supplied to the core memory enable operations such as read/program/erase with respect to cells in the core memory.

公开(公告)号：US09595336B2

公开(公告)日：2017-03-14

申请号：US14926484

申请日：2015-10-29

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Hyoung Seub Rhie

IPC: G11C16/16 ,  G11C16/04 ,  G11C16/14

CPC classification number: G11C16/16 ,  G11C16/0483 ,  G11C16/14

Abstract: A three-dimensional integrated circuit non-volatile memory array includes a memory array with multiple vertical gate NAND memory cell strings formed in a different vertical layers over a substrate which share a common set of word lines, where different groupings of NAND memory cell strings formed between dedicated pairings of source line structures and bit line structures form separately erasable blocks which are addressed and erased by applying an erase voltage to the source line structure of the erase block being erased while applying a ground voltage to the other source line structures in the array and a high pass voltage to the bit line structures in the array.

Abstract translation: 三维集成电路非易失性存储器阵列包括具有多个垂直栅极NAND存储器单元串的存储器阵列，该多个垂直栅极NAND存储器单元串形成在共享一组公共字线的衬底上的不同垂直层中，其中形成了不同的NAND存储器单元串组 在源线结构和位线结构的专用配对之间形成单独的可擦除块，其通过向擦除块擦除块的源极线结构施加擦除电压来寻址和擦除，同时向阵列中的其它源极线结构施加接地电压 以及对阵列中的位线结构的高通电压。

公开(公告)号：US09570123B2

公开(公告)日：2017-02-14

申请号：US14531432

申请日：2014-11-03

Applicant: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.

Inventor： Jin-Ki Kim

IPC: G11C7/10 ,  G11C5/02 ,  G11C7/12 ,  G11C16/24 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16

CPC classification number: G06F3/061 ,  G06F3/0629 ,  G06F3/0659 ,  G06F3/0679 ,  G11C5/025 ,  G11C7/1006 ,  G11C7/1033 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/12 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24 ,  G11C16/26 ,  G11C16/32 ,  G11C2207/107 ,  G11C2216/14 ,  G11C2216/20 ,  G11C2216/30

Abstract: A memory system having a serial data interface and a serial data path core for receiving data from and for providing data to at least one memory bank as a serial bitstream. The memory bank is divided into two halves, where each half is divided into upper and lower sectors. Each sector provides data in parallel to a shared two-dimensional page buffer with an integrated self column decoding circuit. A serial to parallel data converter within the memory bank couples the parallel data from either half to the serial data path core. The shared two-dimensional page buffer with the integrated self column decoding circuit minimizes circuit and chip area overhead for each bank, and the serial data path core reduces chip area typically used for routing wide data buses. Therefore a multiple memory bank system is implemented without a significant corresponding chip area increase when compared to a single memory bank system having the same density.

Abstract translation: 一种具有串行数据接口和串行数据路径核心的存储器系统，用于从至少一个存储器组接收数据并将数据作为串行比特流提供给至少一个存储体。 记忆库分为两半，每半部分分为上下扇区。 每个扇区使用集成的自列解码电路并行提供与共享的二维页面缓冲器的数据。 存储器中的串行到并行数据转换器将并行数据从一半耦合到串行数据路径核心。 具有集成自列解码电路的共享二维页面缓冲器使每个存储体的电路和芯片面积开销最小化，并且串行数据通道内核减少了通常用于布线宽数据总线的芯片面积。 因此，与具有相同密度的单个存储体系统相比，实现多存储体系统而没有显着相应的芯片面积增加。

公开(公告)号：US09524783B2

公开(公告)日：2016-12-20

申请号：US14984303

申请日：2015-12-30

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Hakjune Oh ,  Hong Beom Pyeon ,  Jin-Ki Kim

IPC: G11C7/00 ,  G11C16/10 ,  G11C7/10 ,  G11C16/26 ,  G11C16/06

CPC classification number: G11C11/5628 ,  G06F1/12 ,  G11C7/1021 ,  G11C7/1051 ,  G11C7/1078 ,  G11C11/5642 ,  G11C16/06 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3445 ,  G11C2207/107

Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

Abstract translation: 公开了一种用于控制向半导体存储器中的串行数据链路接口的输出端口传送数据的装置，系统和方法。 在一个示例中，闪存设备可以具有多个串行数据链路，多个存储器组和控制输入端口，其使得存储器设备能够将串行数据传送到存储器件的串行数据输出端口。 在另一示例中，闪存器件可以具有单个串行数据链路，单个存储体，串行数据输入端口，用于接收输出使能信号的控制输入端口。 闪存器件可以使用回波信号线以菊花链配置级联以在存储器件之间串行通信。

公开(公告)号：US20160277027A1

公开(公告)日：2016-09-22

申请号：US15079085

申请日：2016-03-24

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Bruce MILLAR

IPC: H03K19/00 ,  G11C11/4093 ,  H03H17/00

CPC classification number: H03K19/0005 ,  G11C5/063 ,  G11C7/02 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084 ,  G11C11/4093 ,  G11C2207/2254 ,  H03H7/38 ,  H03H17/0045 ,  H04L25/0278 ,  H04L25/028

Abstract: A system and method of performing off chip drive (OCD) and on-die termination (ODT) are provided. A common pull-up network composed of transistors and a common pull-down network composed of transistors are employed to implement both of these functions. In drive mode, the pull-up network is configured to produce a calibrated drive impedance when an “on” output is to be generated, and the pull-up network is configured to produce a calibrated drive impedance when an “off” output is to be generated. In termination mode, the pull-up network and the pull-down network are configured to produce a calibrated pull-up resistance and pull-down resistance respectively such that together, they form a split termination.

公开(公告)号：US20160233224A1

公开(公告)日：2016-08-11

申请号：US14614811

申请日：2015-02-05

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Hyoung Seub Rhie

IPC: H01L27/115

CPC classification number: H01L27/1157 ,  H01L27/11565 ,  H01L27/11582

Abstract: A three-dimensional integrated circuit nonvolatile memory array includes a memory array of vertical channel NAND flash strings connected between an upper layer connection bit line and a substrate which includes one or more elevated source regions disposed on at least one side of each row of NAND flash strings so that each NAND flash string includes a lower select transistor with a first channel portion that runs perpendicular to the surface of the substrate through a vertical channel string body, a second channel portion that runs parallel to the surface of the substrate, and a third channel portion that runs perpendicular to the surface of the substrate through the elevated source region.

Abstract translation: 三维集成电路非易失性存储器阵列包括连接在上层连接位线和衬底之间的垂直通道NAND闪存串的存储器阵列，其包括设置在每行NAND闪存的至少一侧上的一个或多个升高的​​源极区域 使得每个NAND闪存串包括具有第一通道部分的下选择晶体管，第一通道部分通过垂直通道串体垂直于衬底的表面延伸，第二通道部分平行于衬底的表面延伸， 通道部分，其通过升高的源区域垂直于衬底的表面延伸。

公开(公告)号：US09384838B2

公开(公告)日：2016-07-05

申请号：US14590541

申请日：2015-01-06

Applicant: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.

Inventor： Hyoung Seub Rhie

IPC: G11C16/10 ,  G11C16/08 ,  G11C8/08 ,  G11C11/408 ,  G11C16/04

CPC classification number: G11C16/08 ,  G11C8/08 ,  G11C11/4085 ,  G11C16/0483

Abstract: A non-volatile memory device having a memory array organized into a plurality of memory blocks, having either planar memory cells or stacks of cells. Row decoding circuitry of the memory device is configured to select a group of the plurality of memory blocks in response to a first row address, and to select a memory block of the group for receiving row signals in response to a second row address. Row decoding circuitry associated with each group of memory blocks can have a row pitch spacing that is greater than a row pitch spacing of a single memory block and less than or equal to a total row pitch spacing corresponding to the group of memory blocks.

公开(公告)号：US20160141040A1

公开(公告)日：2016-05-19

申请号：US14933264

申请日：2015-11-05

Applicant: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.

Inventor： Chung-Zen CHEN ,  Yang-Chieh LIN ,  Chung-Shan KUO

IPC: G11C16/14 ,  G11C16/04

Abstract: A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal

Abstract translation: 一种非易失性存储器件，包括存储器阵列，该存储器阵列具有被组织为扇区的多个存储器单元，每个扇区具有与多个本地字线相关联的主字线，每个本地字线通过 各自的本地字线驱动电路，每个本地字线驱动电路由耦合在相应主字线和相应本地字线之间的第一MOS晶体管和耦合在相应本地字线和第一 偏置端子

公开(公告)号：US20160071825A1

公开(公告)日：2016-03-10

申请号：US14826251

申请日：2015-08-14

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Byoung Jin CHOI

IPC: H01L25/065 ,  G11C11/401

CPC classification number: H01L25/0657 ,  G11C5/06 ,  G11C7/10 ,  G11C7/1066 ,  G11C7/1093 ,  G11C11/401 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4097 ,  G11C29/023 ,  G11C29/028 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and apparatus for organizing memory for a computer system including a plurality of memory devices, connected to a logic device, particularly a memory system having a plurality of stacked memory dice connected to a logic die, with the logic device having capability to analyze and compensate for differing delays to the stacked devices stacking multiple dice divided into partitions serviced by multiple buses connected to a logic die, to increase throughput between the devices and logic device allowing large scale integration of memory with self-healing capability.

公开(公告)号：US20160064410A1

公开(公告)日：2016-03-03

申请号：US14938259

申请日：2015-11-11

Applicant: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.

Inventor： Hyoung Seub RHIE

IPC: H01L27/115 ,  G11C16/14

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  G11C16/14 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

Abstract: A flash device comprising a well and a U-shaped flash cell string, the U-shaped flash cell string built directly on a substrate adjacent the well. The U-shaped flash cell string comprises one portion parallel to a surface of the substrate, comprising a junctionless bottom pass transistor, and two portions perpendicular to the surface of the substrate that comprise a string select transistor at a first top of the cell string, a ground select transistor at a second top of the cell string, a string select transistor drain, and a ground select transistor source.

Abstract translation: 包括阱和U形闪存单元串的闪存器件，U形闪存单元串直接构建在与阱相邻的衬底上。 U形闪存单元串包括平行于衬底的表面的一个部分，包括无连接底部传输晶体管，以及垂直于衬底表面的两个部分，其包括在电池串的第一顶部的串选择晶体管， 在单元串的第二顶部的接地选择晶体管，串选择晶体管漏极和接地选择晶体管源。