公开(公告)号：US06498391B1

公开(公告)日：2002-12-24

申请号：US09473308

申请日：1999-12-28

申请人： Chien-Ping Huang ,  Lian-Cherng Chiang ,  Michael Chang

发明人： Chien-Ping Huang ,  Lian-Cherng Chiang ,  Michael Chang

IPC分类号： H01L23495

CPC分类号： H01L23/4951 ,  H01L23/3107 ,  H01L23/49575 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48639 ,  H01L2224/48739 ,  H01L2224/48839 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85439 ,  H01L2225/06562 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A dual-chip integrated circuit package with unaligned chip arrangement and a method of manufacturing such a dual-chip integrated circuit package are provided. The dual-chip integrated circuit package includes a leadframe having a first set of leads and a second set of leads. The dual-chip integrated circuit package is used to pack two integrated circuit chips in an unaligned chip arrangement, in which the first integrated circuit chip is mounted to one side of the inner part of the first set of leads, and the second integrated circuit chip is mounted to the other side of the same in such a manner as to allow the bonding pads on the second integrated circuit chip to be positioned in the spacing formed between the two sets of leads. This unaligned chip arrangement can help facilitate the wire-bonding process for the bonding pads are the second integrated circuit chip. An encapsulant is used for encapsulating the first integrated circuit chip, the second integrated circuit chip, the set of bonding wires, the second set of bonding wires, the inner part of the first set of leads, and the inner part of the second set of leads. The particular structure of the dual-chip integrated circuit package allows no restriction to the relative size between first two integrated circuit chips, thus allowing flexible selection for the combination of the two integrated circuit chips. Moreover, the dual-chip integrated circuit package are help save layout space on the circuit board and offers more functionality and storage capacity.

摘要翻译： 提供了具有未对准芯片布置的双芯片集成电路封装以及制造这种双芯片集成电路封装的方法。 双芯片集成电路封装包括具有第一组引线和第二组引线的引线框架。 双芯片集成电路封装用于以未对准的芯片布置来封装两个集成电路芯片，其中第一集成电路芯片安装在第一组引线的内部的一侧，第二集成电路芯片 以这样的方式安装到其另一侧，即允许第二集成电路芯片上的接合焊盘定位在两组引线之间形成的间隔中。 这种未对准的芯片布置可以帮助便于焊接工艺的焊盘是第二个集成电路芯片。 密封剂用于封装第一集成电路芯片，第二集成电路芯片，一组接合线，第二组接合线，第一组引线的内部和第二组引线的内部 领导。 双芯片集成电路封装的特定结构不限制前两个集成电路芯片之间的相对尺寸，从而允许灵活地选择两个集成电路芯片的组合。 此外，双芯片集成电路封装有助于节省电路板上的布局空间，并提供更多的功能和存储容量。

公开(公告)号：US06437447B1

公开(公告)日：2002-08-20

申请号：US09697296

申请日：2000-10-27

申请人： Chien-Ping Huang ,  Chin-Yuan Hung ,  Chang-Fu Chen ,  Jenn-Shyh Yu ,  Jui-Hsiang Hung

发明人： Chien-Ping Huang ,  Chin-Yuan Hung ,  Chang-Fu Chen ,  Jenn-Shyh Yu ,  Jui-Hsiang Hung

IPC分类号： H01L2348

CPC分类号： H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： In a dual-sided chip package without a die pad according to the invention, a first die can be fixed directly on the lead fingers of a leadframe, a support bar, or bus bars, while a second die is attached to the first die. Without a die pad, the distance between the surfaces of the dies and the plastic surface of the package therefore gets longer. Thus, the invention enables a large decrease in the probability of generating voids in the plastic and there is no need to grind the dies. Besides, it improves the vibration and floating characteristics of the dies in the manufacturing process and thus prevents the exposure of the bonding wires and the shelling off or breaking of the dies. The invention can raise the yield of chip packages.

摘要翻译： 在根据本发明的没有芯片焊盘的双面芯片封装中，第一裸片可以直接固定在引线框架，支撑杆或汇流条的引线上，而第二裸片附接到第一裸片。 没有管芯焊盘，因此，模具表面与封装的塑料表面之间的距离变长。 因此，本发明能够大大降低在塑料中产生空隙的可能性，并且不需要研磨模具。 此外，在制造过程中，提高了模具的振动和浮动特性，防止了接合线的暴露和模具脱壳或断裂。 本发明可以提高芯片封装的产量。

公开(公告)号：US06396707B1

公开(公告)日：2002-05-28

申请号：US09454006

申请日：1999-12-03

申请人： Chien-Ping Huang ,  Grace Yang

发明人： Chien-Ping Huang ,  Grace Yang

IPC分类号： H05K702

CPC分类号： H01L23/49816 ,  H01L2924/0002 ,  H05K3/3452 ,  H05K3/3457 ,  H05K2201/0989 ,  H01L2924/00

摘要： A ball grid array package comprises a substrate having a first surface and a second surface, a chip, an insulating material, and a solder ball. The surface of the substrate comprises ball pads, conducting traces, and solder masks wherein the conducting traces are disposed in between the adjacent ball pads, and are covered by the solder mask, in addition, a portion of each of the ball pads is also covered by the solder mask. The solder mask includes an opening positioned in the area corresponding to the ball pads wherein the opening exposes a portion of the surface the ball pad and a portion of the side wall of the ball pad. The chip is disposed on the second surface of the substrate, and is sealed and encapsulated by the insulated material. The solder balls are disposed on the first surface of the substrate, and are positioned at the openings of the ball pads. Additionally, the solder balls are electrically connected to a portion of the surface of the ball pads and a portion of the side wall of the ball pads disposed at the ball pad openings.

摘要翻译： 球栅阵列封装包括具有第一表面和第二表面的衬底，芯片，绝缘材料和焊球。 衬底的表面包括球垫，导电迹线和焊接掩模，其中导电迹线设置在相邻的球垫之间，并被焊接掩模覆盖，此外，每个球垫的一部分也被覆盖 通过焊接面罩。 焊接掩模包括位于对应于球垫的区域中的开口，其中开口暴露表面的一部分球垫和球垫的侧壁的一部分。 芯片设置在基板的第二表面上，并被绝缘材料密封和封装。 焊球设置在基板的第一表面上，并且位于球垫的开口处。 此外，焊球与电极焊盘表面的一部分电连接，球垫侧壁的一部分设置在球垫开口处。

公开(公告)号：US06350669B1

公开(公告)日：2002-02-26

申请号：US09699888

申请日：2000-10-30

申请人： Han-Ping Pu ,  Chien-Ping Huang

发明人： Han-Ping Pu ,  Chien-Ping Huang

IPC分类号： H01L2144

CPC分类号： H01L24/11 ,  H01L21/4846 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/14505 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H05K3/3436 ,  H05K3/3463 ,  H05K2201/094 ,  H05K2201/10234 ,  H05K2201/10992 ,  H05K2203/041 ,  Y02P70/613 ,  H01L2224/05599

摘要： A method is proposed for bonding a BGA (Ball Grid Array) package to a circuit board without causing the collapsing of the BGA package against the circuit board. The proposed method is characterized in the use of two groups of solder balls of different reflow collapse degrees, which are arranged in an interspersed manner among each other in the ball grid array. In one embodiment, the first group of solder balls are homogenously made of a solder material of a specific melting point; and the second group of solder balls each include an outer portion and a core portion, with the outer portion having substantially the same melting point as the first group of solder balls, and the core portion being greater in melting point than the outer portion. In another embodiment, the second group of solder balls are greater in melting point than the first group of solder balls. During the solder-reflow process, when the first group of solder balls are entirely melted, the second group of solder balls are only partly melted or entirely unmelted and thus are capable of providing a solid support to the BGA package to prevent the collapsing of BGA package against circuit board.

摘要翻译： 提出了一种用于将BGA（球栅阵列）封装结合到电路板而不引起BGA封装相对于电路板折叠的方法。 所提出的方法的特征在于使用不同回流塌陷度的两组焊球，其在球栅阵列中以散布的方式相互排列。 在一个实施例中，第一组焊球由具有特定熔点的焊料均质地制成; 并且第二组焊球各自包括外部部分和芯部分，外部部分具有与第一组焊球基本相同的熔点，并且芯部分的熔点大于外部部分。 在另一个实施例中，第二组焊球的熔点高于第一组焊球。 在焊料回流工艺期间，当第一组焊球完全熔化时，第二组焊球仅部分熔化或完全未熔化，因此能够为BGA封装提供固体支撑以防止BGA的塌陷 封装电路板。

公开(公告)号：US06306682B1

公开(公告)日：2001-10-23

申请号：US09547157

申请日：2000-04-11

申请人： Chien-Ping Huang ,  Randy H. Y. Lo ,  Tzong-Da Ho ,  Eric Ko ,  Jui-Meng Jao

发明人： Chien-Ping Huang ,  Randy H. Y. Lo ,  Tzong-Da Ho ,  Eric Ko ,  Jui-Meng Jao

IPC分类号： H01L2144

CPC分类号： H01L21/56 ,  H01L23/3128 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： A method of fabricating a BGA (Ball Grid Array) IC package of the type having an encapsulating body is proposed, which allows the BGA IC package to be manufactured without having to use conventional organic substrate and encapsulating-body mold having cavity, so that the manufacture process can be more cost-effective to carry out than the prior art. The proposed method is characterized in the use of a copper piece which is selectively removed to form an encapsulating-body cavity for the forming of an encapsulating body therein. The proposed method requires no use of mold with cavity for the forming of the encapsulating body, allowing the same mold to be used for the fabrication of various BGA IC packages of different sizes. Moreover, the proposed method allows fan-in design as well as fan-out design, thus allowing the number of I/O ports to be increased while making the overall package configuration compact in size, and also allows the implantation of the electrically-conductive balls to be easier to carry out and more precisely controlled than the prior art, making the ball implantation more assured in quality than the prior art. Therefore, the proposed method is more advantageous and cost-effective to use than the prior art.

摘要翻译： 提出了一种制造具有封装体的BGA（球栅阵列）IC封装的方法，其允许制造BGA IC封装，而不必使用传统的有机衬底和具有空腔的封装体模具， 制造工艺比现有技术更具成本效益。 所提出的方法的特征在于使用铜片，其被选择性地去除以形成用于在其中形成封装体的封装体腔体。 所提出的方法不需要使用具有空腔的模具来形成封装体，允许相同的模具用于制造不同尺寸的各种BGA IC封装。 此外，所提出的方法允许风扇设计以及扇出式设计，从而允许增加I / O端口的数量，同时使整个封装结构的尺寸紧凑，并且还允许将导电 球比现有技术更容易实施和更精确地控制，使得球注入在质量上比现有技术更加确保。 因此，所提出的方法比现有技术更有利且成本有效。

公开(公告)号：US06290481B1

公开(公告)日：2001-09-18

申请号：US09574878

申请日：2000-05-19

申请人： Chien-Ping Huang

发明人： Chien-Ping Huang

IPC分类号： B29C4514

CPC分类号： B29C45/2701 ,  H01L21/565 ,  H01L2924/0002 ,  H01L2924/00

摘要： A flash-free mold structure is designed for use in the molding of an encapsulant for encapsulating a semiconductor die. The flash-free mold structure includes a first molding piece and a second molding piece. The second molding piece is formed with a resin passage for an encapsulating material to flow therethrough during molding process. It is a characteristic feature of this flash-free mold structure that a cutaway portion, which can be either an one-step cutaway portion or a multi-step cutaway portion, is formed at the rim of the resin passage. The cutaway portion is dimensioned significantly smaller than the resin passage for the retarding the flow speed of the encapsulating material from the resin passage into the cutaway portion during the molding process, thereby preventing the encapsulating material from entering the fissure in the junction between the first and second molding pieces. The resin passage can be either a cull, a runner, or a subrunner defined by the first and second molding pieces. With this flash-free mold structure, the IC packaging quality can be assured and fabrication tools can be prevented from contamination.

摘要翻译： 无闪光模具结构被设计用于模制用于封装半导体管芯的密封剂。 无闪光模具结构包括第一成型件和第二成型件。 第二成型件在模制过程中由用于密封材料的树脂通道形成为流过其中。 这种无闪光模具结构的特征在于，在树脂通道的边缘处形成有可以是一步切口部分或多段切口部分的切口部分。 切割部分的尺寸明显小于树脂通道，用于在模制过程中阻止封装材料从树脂通道进入切除部分的流动速度，从而防止封装材料在第一和第二部分之间的接合处进入裂缝 第二个成型件。 树脂通道可以是由第一和第二成型件限定的剔除，流道或辅助材料。 利用这种无闪光模具结构，可以确保IC封装质量，并可防止制造工具的污染。

公开(公告)号：US08546183B2

公开(公告)日：2013-10-01

申请号：US12241847

申请日：2008-09-30

申请人： Chien-Ping Huang ,  Chih-Ming Huang

发明人： Chien-Ping Huang ,  Chih-Ming Huang

IPC分类号： H01L21/02

CPC分类号： H01L23/3677 ,  H01L21/4871 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/3733 ,  H01L23/4334 ,  H01L23/49548 ,  H01L23/49816 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/351 ,  Y10T29/49126 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A heat dissipating semiconductor package and a fabrication method thereof are provided. A semiconductor chip is mounted on a chip carrier. A heat sink is mounted on the chip, and includes an insulating core layer, a thin metallic layer formed on each of an upper surface and a lower surface of the insulating core layer and a thermal via hole formed in the insulating core layer. A molding process is performed to encapsulate the chip and the heat sink with an encapsulant to form a package unit. A singulation process is performed to peripherally cut the package unit. A part of the encapsulant above the thin metallic layer on the upper surface of the heat sink is removed, such that the thin metallic layer on the upper surface of the heat sink is exposed, and heat generated by the chip can be dissipated through the heat sink.

摘要翻译： 提供散热半导体封装及其制造方法。 半导体芯片安装在芯片载体上。 散热器安装在芯片上，并且包括绝缘芯层，形成在绝缘芯层的上表面和下表面中的每一个上的薄金属层和形成在绝缘芯层中的热通孔。 进行成型工艺以用密封剂封装芯片和散热器以形成封装单元。 执行单个处理以周边地切割包装单元。 在散热器的上表面上的薄金属层上方的一部分密封剂被去除，使得散热器上表面上的薄金属层被暴露，并且由芯片产生的热量可以通过热量散发 水槽。

公开(公告)号：US20130063059A1

公开(公告)日：2013-03-14

申请号：US13589936

申请日：2012-08-20

申请人： Chien-Yu Chi ,  Chien-Ping Huang

发明人： Chien-Yu Chi ,  Chien-Ping Huang

IPC分类号： H02P6/14

CPC分类号： H02P27/08 ,  H02M2001/385

摘要： Proposed is a driver having dead-time compensation function. The driver having dead-time compensation function generates an output voltage according to a voltage command and a frequency command. The driver includes an inverter, an output current detector and a control unit. The inverter receives a DC voltage and operates with a pulse width modulation mode so that the driver outputs the output voltage and an output current. The output current detector detects the current value of the output current to generate a output current detecting signal. The control unit outputs a switching control signal to inverter according to the voltage command and the frequency command. The control unit corrects a reference command according to dead-time and the output current detecting signal related to the output current so that amplitude and waveform smoothness of the output voltage and the output current are compensated.

摘要翻译： 建议是具有死区补偿功能的驾驶员。 具有死区补偿功能的驱动器根据电压指令和频率指令产生输出电压。 驱动器包括逆变器，输出电流检测器和控制单元。 逆变器接收直流电压并以脉冲宽度调制模式工作，以便驱动器输出输出电压和输出电流。 输出电流检测器检测输出电流的当前值以产生输出电流检测信号。 控制单元根据电压指令和频率指令向逆变器输出切换控制信号。 控制单元根据死区时间和与输出电流相关的输出电流检测信号来校正参考命令，从而补偿输出电压和输出电流的振幅和波形平滑度。

公开(公告)号：US20110227226A1

公开(公告)日：2011-09-22

申请号：US13151823

申请日：2011-06-02

申请人： Chiang-Cheng Chiang ,  Chien-Ping Huang ,  Chin-Huang Chang ,  Chi-Hsin Chiu ,  Jung-Pin Huang

发明人： Chiang-Cheng Chiang ,  Chien-Ping Huang ,  Chin-Huang Chang ,  Chi-Hsin Chiu ,  Jung-Pin Huang

IPC分类号： H01L23/48

CPC分类号： H01L29/0657 ,  H01L23/481 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05568 ,  H01L2224/14181 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/05599

摘要： The invention discloses a multi-chip stack structure having through silicon via and a method for fabricating the same. The method includes: providing a wafer having a plurality of first chips; forming a plurality of holes on a first surface of each of the first chips and forming metal posts and solder pads corresponding to the holes so as to form a through silicon via (TSV) structure; forming at least one groove on a second surface of each of the first chips to expose the metal posts of the TSV structure so as to allow at least one second chip to be stacked on the first chip, received in the groove and electrically connected to the metal posts exposed from the groove; filling the groove with an insulating material for encapsulating the second chip; mounting conductive elements on the solder pads of the first surface of each of the first chips and singulating the wafer; and mounting and electrically connecting the stacked first and second chips to a chip carrier via the conductive elements. The wafer, which is not totally thinned but includes a plurality of first chips, severs a carrying purpose during the fabrication process and thereby solves problems, namely a complicated process, high cost, and adhesive layer contamination, facing the prior art that entails repeated use of a carrier board and an adhesive layer for vertically stacking a plurality of chips and mounting the stacked chips on a chip carrier.

摘要翻译： 本发明公开了一种通过硅通孔的多芯片堆叠结构及其制造方法。 该方法包括：提供具有多个第一芯片的晶片; 在每个所述第一芯片的第一表面上形成多个孔，并形成对应于所述孔的金属柱和焊盘，以形成贯穿硅通孔（TSV）结构; 在所述第一芯片的每一个的第二表面上形成至少一个凹槽以暴露所述TSV结构的所述金属柱，以允许至少一个第二芯片堆叠在所述第一芯片上，被接收在所述凹槽中并电连接到 从槽露出的金属柱; 用绝缘材料填充凹槽以封装第二芯片; 将导电元件安装在每个第一芯片的第一表面的焊盘上并分离晶片; 并且经由导电元件将堆叠的第一和第二芯片安装并电连接到芯片载体。 不是完全变薄但包括多个第一芯片的晶片在制造过程中切断了承载目的，从而解决了面临现有技术需要重复使用的问题，即复杂的工艺，高成本和粘合剂层污染 的载体板和用于垂直堆叠多个芯片的粘合剂层，并将堆叠的芯片安装在芯片载体上。

公开(公告)号：US08013443B2

公开(公告)日：2011-09-06

申请号：US12727307

申请日：2010-03-19

申请人： Fang-Lin Tsai ,  Ho-Yi Tsai ,  Chih-Ming Huang ,  Chien-Ping Huang

发明人： Fang-Lin Tsai ,  Ho-Yi Tsai ,  Chih-Ming Huang ,  Chien-Ping Huang

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/3121 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/3025 ,  H05K3/284 ,  H05K3/3442 ,  H05K3/3452 ,  H05K2201/0989 ,  H05K2201/10636 ,  Y02P70/611 ,  H01L2924/00

摘要： An electronic carrier board and a package structure thereof are provided. The electronic carrier board includes a carrier, at least one pair of bond pads formed on the carrier, and a protective layer covering the carrier. The protective layer is formed with openings for exposing the bond pads. A groove is formed between the paired bond pads and has a length larger than a width of an electronic component mounted on the paired bond pads. The groove is adjacent to one of the paired bond pads and communicates with a corresponding one of the openings where this bond pad is exposed. Accordingly, a clearance between the electronic component and the electronic carrier board can be effectively filled with an insulating resin for encapsulating the electronic component, thereby preventing voids and undesirable electrical bridging between the paired bond pads from occurrence.

摘要翻译： 提供电子载体板及其封装结构。 电子载板包括载体，形成在载体上的至少一对接合焊盘和覆盖载体的保护层。 保护层形成有用于暴露接合焊盘的开口。 在成对的接合焊盘之间形成有一个沟槽，其长度大于安装在成对接合焊盘上的电子部件的宽度。 该沟槽与一对接合焊盘相邻，并与该接合焊盘露出的相应的一个开口连通。 因此，电子部件和电子载体板之间的间隙可以有效地填充用于封装电子部件的绝缘树脂，从而防止成对焊盘之间的空隙和不期望的电桥发生。