READ OPERATION FOR NON-VOLATILE STORAGE THAT INCLUDES COMPENSATION FOR COUPLING

    公开(公告)号:US20070103975A1

    公开(公告)日:2007-05-10

    申请号:US11616769

    申请日:2006-12-27

    申请人: Yan Li Jian Chen

    发明人: Yan Li Jian Chen

    IPC分类号: G11C16/04

    摘要: Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. To compensate for this coupling, the read process for a given memory cell will take into account the programmed state of an adjacent memory cell.

    Polynucleotides encoding a human cell surface protein with immunoglobulin folds, BGS-19
    103.
    发明授权
    Polynucleotides encoding a human cell surface protein with immunoglobulin folds, BGS-19 有权
    编码具有免疫球蛋白折叠的人细胞表面蛋白的多核苷酸,BGS-19

    公开(公告)号:US07202056B2

    公开(公告)日:2007-04-10

    申请号:US10403938

    申请日:2003-03-28

    摘要: The present invention provides novel polynucleotides encoding BGS-19 polypeptides, fragments and homologues thereof. Also provided are vectors, host cells, antibodies, and recombinant and synthetic methods for producing said polypeptides. The invention further relates to diagnostic and therapeutic methods for applying the novel BGS-19 polypeptides to the diagnosis, treatment, and/or prevention of various diseases and/or disorders related to these polypeptides. The invention further relates to screening methods for identifying agonists and antagonists of the polynucleotides and polypeptides of the present invention.

    摘要翻译: 本发明提供了编码BGS-19多肽的新型多核苷酸,其片段和同源物。 还提供了载体,宿主细胞,抗体以及用于产生所述多肽的重组和合成方法。 本发明还涉及将新型BGS-19多肽应用于诊断,治疗和/或预防与这些多肽相关的各种疾病和/或病症的诊断和治疗方法。 本发明还涉及用于鉴定本发明的多核苷酸和多肽的激动剂和拮抗剂的筛选方法。

    Novel human cell surface protein with immunoglobulin folds, BGS-19
    104.
    发明申请
    Novel human cell surface protein with immunoglobulin folds, BGS-19 审中-公开
    具有免疫球蛋白折叠的新型人细胞表面蛋白BGS-19

    公开(公告)号:US20070071743A1

    公开(公告)日:2007-03-29

    申请号:US11601407

    申请日:2006-11-17

    摘要: The present invention provides novel polynucleotides encoding BGS-19 polypeptides, fragments and homologues thereof. Also provided are vectors, host cells, antibodies, and recombinant and synthetic methods for producing said polypeptides. The invention further relates to diagnostic and therapeutic methods for applying the novel BGS-19 polypeptides to the diagnosis, treatment, and/or prevention of various diseases and/or disorders related to these polypeptides. The invention further relates to screening methods for identifying agonists and antagonists of the polynucleotides and polypeptides of the present invention.

    摘要翻译: 本发明提供了编码BGS-19多肽的新型多核苷酸,其片段和同源物。 还提供了载体,宿主细胞,抗体以及用于产生所述多肽的重组和合成方法。 本发明还涉及将新型BGS-19多肽应用于诊断,治疗和/或预防与这些多肽相关的各种疾病和/或病症的诊断和治疗方法。 本发明还涉及用于鉴定本发明的多核苷酸和多肽的激动剂和拮抗剂的筛选方法。

    Read and erase verify methods and circuits suitable for low voltage non-volatile memories
    105.
    发明申请
    Read and erase verify methods and circuits suitable for low voltage non-volatile memories 有权
    读取和擦除适用于低电压非易失性存储器的验证方法和电路

    公开(公告)号:US20070058435A1

    公开(公告)日:2007-03-15

    申请号:US10552948

    申请日:2004-04-08

    IPC分类号: G11C11/34

    摘要: In a non-volatile memory, the read parameter used to distinguish the data states characterized by a negative threshold voltage from the data states characterized by a positive threshold voltage is compensated for the memory's operating conditions, rather than being hardwired to ground. In an exemplary embodiment, the read parameter for the data state with the lowest threshold value above ground is temperature compensated to reflect the shifts of the storage element populations on either side of the read parameter. According to another aspect, an erase process is presented that can take advantage the operating condition compensated sensing parameter. As the sensing parameter is no longer fixed at a value corresponding to 0 volts, instead shifting according to operating conditions, a sufficient margin is provided for the various erase verify levels even at lowered operating voltages.

    摘要翻译: 在非易失性存储器中,用于区分由负阈值电压表征的数据状态的读取参数与由正阈值电压表征的数据状态进行补偿,而不是硬连线到地。 在示例性实施例中,对于具有高于地面的最低阈值的数据状态的读取参数被温度补偿以反映存储元件群在读取参数的任一侧上的偏移。 根据另一方面,提出了可以利用操作条件补偿的感测参数的擦除过程。 由于感测参数不再固定为对应于0伏的值,而是根据工作条件进行移位,即使在降低的工作电压下,也为各种擦除验证电平提供足够的余量。

    Use of nanoparticles in film formation and as solder
    106.
    发明申请
    Use of nanoparticles in film formation and as solder 审中-公开
    在成膜和焊料中使用纳米颗粒

    公开(公告)号:US20070044295A1

    公开(公告)日:2007-03-01

    申请号:US11432553

    申请日:2006-05-12

    申请人: Jian Chen

    发明人: Jian Chen

    IPC分类号: H01S4/00

    摘要: Nanoparticle compositions for use as solder, and methods for joining two or more material surfaces using nanoparticle solder compositions are described. Due to their small size, nanoparticles of a particular material have a lower melting temperature than the same material in bulk, thereby providing a homogenous bond between two or more materials when the nanoparticle solder is solidified. A gas species, such as hydrogen, can be introduced to further lower the melting temperature of the nanoparticles. The nanoparticles can also be used to form films on low melting point, substrates, including flexible substrates. The nanoparticles for use in the present invention can comprise any material, including semiconductor materials, metals, or insulator materials, and are less than about 20 nm in diameter, although larger sizes can also be used.

    摘要翻译: 描述了用作焊料的纳米颗粒组合物,以及使用纳米颗粒焊料组合物连接两个或多个材料表面的方法。 由于其小的尺寸,特定材料的纳米颗粒具有比同体材料更低的熔融温度,从而当纳米颗粒焊料固化时,在两种或多种材料之间提供均匀的结合。 可以引入气体物质,例如氢气,以进一步降低纳米颗粒的熔融温度。 纳米颗粒也可用于在低熔点,底物(包括柔性基底)上形成薄膜。 用于本发明的纳米颗粒可以包括任何材料,包括半导体材料,金属或绝缘体材料,并且直径小于约20nm,尽管也可以使用更大的尺寸。

    Selective operation of a multi-state non-volatile memory system in a binary mode
    107.
    发明授权
    Selective operation of a multi-state non-volatile memory system in a binary mode 有权
    以二进制模式选择性地操作多状态非易失性存储器系统

    公开(公告)号:US07177184B2

    公开(公告)日:2007-02-13

    申请号:US10818926

    申请日:2004-04-05

    申请人: Jian Chen

    发明人: Jian Chen

    IPC分类号: G11C16/04

    摘要: A flash non-volatile memory system that normally operates its memory cells in multiple storage states is provided with the ability to operate some selected or all of its memory cell blocks in two states instead. The two states are selected to be the furthest separated of the multiple states, thereby providing an increased margin during two state operation. This allows faster programming and a longer operational life of the memory cells being operated in two states when it is more desirable to have these advantages than the increased density of data storage that multi-state operation provides.

    摘要翻译: 具有通常在多个存储状态下操作其存储器单元的闪存非易失性存储器系统具有以两种状态操作其一些所选或全部存储单元块的能力。 两个状态被选择为多个状态中最远的分离状态,从而在两个状态操作期间提供增加的余量。 这允许当多状态操作提供的数据存储器的密度增加时更有希望具有这些优点时,更快的编程和较长的存储器单元的操作寿命处于两种状态。

    Method of semiconductor fabrication incorporating disposable spacer into elevated source/drain processing
    110.
    发明授权
    Method of semiconductor fabrication incorporating disposable spacer into elevated source/drain processing 有权
    将一次性间隔件加入升高的源/漏处理的半导体制造方法

    公开(公告)号:US07125805B2

    公开(公告)日:2006-10-24

    申请号:US10839385

    申请日:2004-05-05

    摘要: A semiconductor fabrication process includes forming a gate electrode overlying a substrate. A first silicon nitride spacer is formed adjacent the gate electrode sidewalls and a disposable silicon nitride spacer is then formed adjacent the offset spacer. An elevated source/drain structure, defined by the boundaries of the disposable spacer, is then formed epitaxially. The disposable spacer is then removed to expose the substrate proximal to the gate electrode and a shallow implant, such as a halo or extension implant, is introduced into the exposed substrate proximal the gate electrode. A replacement spacer is formed substantially where the disposable spacer existed a source/drain implant is done to introduce a source/drain impurity distribution into the elevated source drain. The gate electrode may include an overlying silicon nitride capping layer and the first silicon nitride spacer may contact the capping layer to surround the polysilicon gate electrode in silicon nitride.

    摘要翻译: 半导体制造工艺包括形成覆盖衬底的栅电极。 在栅电极侧壁附近形成第一氮化硅间隔物,然后在偏移间隔物附近形成一次性氮化硅间隔物。 然后由一次性间隔件的边界限定的升高的源极/漏极结构外延形成。 然后去除一次性间隔件以暴露基板靠近栅电极,并且将浅的植入物(例如晕或延伸植入物)引入靠近栅电极的暴露的基底中。 基本上形成替代间隔物,其中一次性间隔物存在,进行源极/漏极注入以将源极/漏极杂质分布引入升高的源极漏极。 栅电极可以包括上覆的氮化硅覆盖层,并且第一氮化硅间隔物可接触覆盖层以在氮化硅中包围多晶硅栅电极。