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    Warpage control for microelectronics packages
    103.
    发明授权
    Warpage control for microelectronics packages 有权

    公开(公告)号：US11114388B2

    公开(公告)日：2021-09-07

    申请号：US16280993

    申请日：2019-02-20

    Applicant: INTEL CORPORATION

    Inventor： Eric J. Li ,  Guotao Wang ,  Huiyang Fei ,  Sairam Agraharam ,  Omkar G. Karhade ,  Nitin A. Deshpande

    IPC: H01L23/52 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H05K3/30 ,  H05K3/34 ,  H05K1/18 ,  H01L21/48

    Abstract: Techniques for reducing warpage for microelectronic packages are provided. A warpage control layer or stiffener can be attached to a bottom surface of a substrate or layer that is used to attach the microelectronics package to a motherboard. The warpage control layer can have a thickness approximately equal to a thickness of a die of the microelectronics package. A coefficient of thermal expansion of the warpage control layer can be selected to approximately match a CTE of the die. The warpage control layer can be formed from an insulating material or a metallic material. The warpage control layer can comprise multiple materials and can include copper pillar segments to adjust the effective CTE of the warpage control layer. The warpage control layer can be positioned between the microelectronics package and the motherboard, thereby providing warpage control without contributing to the z-height of the microelectronics package.

    Embedded multi-device bridge with through-bridge conductive via signal connection
    105.
    发明授权
    Embedded multi-device bridge with through-bridge conductive via signal connection 有权

    公开(公告)号：US10797000B2

    公开(公告)日：2020-10-06

    申请号：US16254126

    申请日：2019-01-22

    Applicant: INTEL CORPORATION

    Inventor： Nitin A. Deshpande ,  Omkar G. Karhade

    IPC: H01L23/538 ,  H01L25/065 ,  H01L25/00 ,  H01L23/13 ,  H01L23/522 ,  H01L21/48 ,  H01L23/00

    Abstract: A microelectronic structure includes a substrate having a first surface and a cavity extending into the substrate from the substrate first surface, a first microelectronic device and a second microelectronic device attached to the substrate first surface, and a bridge disposed within the substrate cavity and attached to the first microelectronic device and to the second microelectronic device. The bridge includes a plurality conductive vias extending from a first surface to an opposing second surface of the bridge, wherein the conductive vias are electrically coupled to deliver electrical signals from the substrate to the first microelectronic device and the second microelectronic device. The bridge further creates at least one electrical signal connection between the first microelectronic device and the second microelectronic device.

    Low cost package warpage solution
    106.
    发明授权
    Low cost package warpage solution 有权

    公开(公告)号：US10403512B2

    公开(公告)日：2019-09-03

    申请号：US15899222

    申请日：2018-02-19

    Applicant: Intel Corporation

    Inventor： Omkar G. Karhade ,  Nitin A. Deshpande ,  Debendra Mallik ,  Bassam M. Ziadeh ,  Yoshihiro Tomita

    IPC: H01L21/56 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H01L23/16

    Abstract: Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.

    Integrated circuit package with embedded bridge
    107.
    发明授权
    Integrated circuit package with embedded bridge 有权

    公开(公告)号：US10068852B2

    公开(公告)日：2018-09-04

    申请号：US15636117

    申请日：2017-06-28

    Applicant: Intel Corporation

    Inventor： Ravindranath V. Mahajan ,  Christopher J. Nelson ,  Omkar G. Karhade ,  Feras Eid ,  Nitin A. Deshpande ,  Shawna M. Liff

    IPC: H01L23/538 ,  H01L25/065 ,  H01L23/367 ,  H01L23/31

    Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package having first and second dies with first and second input/output (I/O) interconnect structures, respectively. The IC package may include a bridge having first and second electrical routing features coupled to a portion of the first and second I/O interconnect structures, respectively. In embodiments, the first and second electrical routing features may be disposed on one side of the bridge; and third electrical routing features may be disposed on an opposite side. The first and second electrical routing features may be configured to route electrical signals between the first die and the second die and the third electrical routing features may be configured to route electrical signals between the one side and the opposite side. The first die, the second die, and the bridge may be embedded in electrically insulating material. Other embodiments may be described and/or claimed.

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