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    Design Structures Incorporating Semiconductor Device Structures with Reduced Junction Capacitance and Drain Induced Barrier Lowering
    101.
    发明申请
    Design Structures Incorporating Semiconductor Device Structures with Reduced Junction Capacitance and Drain Induced Barrier Lowering 有权
    结合具有减少的结电容和漏极诱导的阻挡层的半导体器件结构的设计结构

    公开(公告)号：US20080034335A1

    公开(公告)日：2008-02-07

    申请号：US11875013

    申请日：2007-10-19

    申请人： Kangguo Cheng ,  Louis Hsu ,  Jack Mandelman ,  Haining Yang

    发明人： Kangguo Cheng ,  Louis Hsu ,  Jack Mandelman ,  Haining Yang

    IPC分类号： G11C29/54

    CPC分类号： H01L29/78603 ,  G11C29/54 ,  H01L29/51 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66772

    摘要： Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes semiconductor device structures characterized by reduced junction capacitance and drain induced barrier lowering. The semiconductor device structure of the design structure includes a semiconductor layer and a dielectric layer disposed between the semiconductor layer and the substrate. The dielectric layer includes a first dielectric region with a first dielectric constant and a second dielectric region with a second dielectric constant that is greater than the first dielectric constant.

    摘要翻译： 用于设计，制造或测试设计的机器可读介质中体现的设计结构。 该设计结构包括半导体器件结构，其特征在于结电容减小和漏极引起的栅极降低。 设计结构的半导体器件结构包括设置在半导体层和衬底之间的半导体层和介电层。 电介质层包括具有第一介电常数的第一电介质区域和具有大于第一介电常数的第二介电常数的第二电介质区域。

    STRUCTURE AND METHOD OF FABRICATING A HINGE TYPE MEMS SWITCH
    103.
    发明申请
    STRUCTURE AND METHOD OF FABRICATING A HINGE TYPE MEMS SWITCH 失效
    铰链类型MEMS开关的结构和方法

    公开(公告)号：US20080014663A1

    公开(公告)日：2008-01-17

    申请号：US11776835

    申请日：2007-07-12

    申请人： Louis Hsu ,  Timothy Dalton ,  Lawrence Clevenger ,  Carl Radens ,  Kwong Wong ,  Chih-Chao Yang

    发明人： Louis Hsu ,  Timothy Dalton ,  Lawrence Clevenger ,  Carl Radens ,  Kwong Wong ,  Chih-Chao Yang

    IPC分类号： H01L21/00

    CPC分类号： H01H59/0009 ,  H01H1/20 ,  H01H2001/0084 ,  H01H2001/0089 ,  Y10T29/49105 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49204 ,  Y10T29/49208

    摘要： A hinge type MEMS switch that is fully integratable within a semiconductor fabrication process such as a CMOS, is described. The MEMS switch constructed on a substrate consists of two posts, each end thereof terminating in a cap; a rigid movable conductive plate having a surface terminating in a ring in each of two opposing edges, the rings being loosely connected to guiding posts; upper and lower electrode pairs; and upper and lower interconnect wiring lines connected and disconnected by the rigid movable conductive plate. When in the energized state, a low voltage level is applied to the upper electrode pair, while the lower electrode pair is grounded. The conductive plate moves up, shorting two upper interconnect wirings lines. Conversely, the conductive plate moves down when the voltage is applied to the lower electrode pair, while the upper electrode pair is grounded, shorting the two lower interconnect wiring lines and opening the upper wiring lines. The MEMS switch thus formed generates an even force that provides the conductive plate with a translational movement, with the displacement being guided by the two vertical posts.

    摘要翻译： 描述了在诸如CMOS之类的半导体制造工艺中可完全集成的铰链式MEMS开关。 构造在基板上的MEMS开关由两个柱构成，每个端部终止于盖; 刚性可移动导电板，其表面终止于两个相对边缘中的每一个中的环中，所述环松散地连接到引导柱; 上下电极对; 并且由刚性可移动导电板连接和断开的上下互连布线。 当处于通电状态时，低电压电平施加到上电极对，而下电极对接地。 导电板向上移动，使两条上部互连线路短路。 相反，当电压施加到下电极对时，导电板向下移动，而上电极对接地，使两个下互连布线短路并打开上布线。 由此形成的MEMS开关产生均匀的力，其为导电板提供平移运动，位移由两个垂直柱引导。

    MODIFIED VIA BOTTOM STRUCTURE FOR RELIABILITY ENHANCEMENT
    105.
    发明申请
    MODIFIED VIA BOTTOM STRUCTURE FOR RELIABILITY ENHANCEMENT 审中-公开
    通过可靠性增强的底部结构进行修改

    公开(公告)号：US20070281469A1

    公开(公告)日：2007-12-06

    申请号：US11839258

    申请日：2007-08-15

    申请人： Lawrence Clevenger ,  Timothy Dalton ,  Louis Hsu ,  Conal Murray ,  Carl Radens ,  Kwong-Hon Wong ,  Chih-Chao Yang

    发明人： Lawrence Clevenger ,  Timothy Dalton ,  Louis Hsu ,  Conal Murray ,  Carl Radens ,  Kwong-Hon Wong ,  Chih-Chao Yang

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76802 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76865 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： The present invention provides an interconnect structure that can be made in the BEOL which exhibits good mechanical contact during normal chip operations and does not fail during various reliability tests as compared with the conventional interconnect structures described above. The inventive interconnect structure has a kinked interface at the bottom of a via that is located within an interlayer dielectric layer. Specifically, the inventive interconnect structure includes a first dielectric layer having at least one metallic interconnect embedded within a surface thereof; a second dielectric layer located atop the first dielectric layer, wherein said second dielectric layer has at least one aperture having an upper line region and a lower via region, wherein the lower via region includes a kinked interface; at least one pair of liners located on at least vertical walls of the at least one aperture; and a conductive material filling the at least one aperture.

    摘要翻译： 本发明提供一种可以在BEOL中制造的互连结构，其在正常的芯片操作期间表现出良好的机械接触，并且在与上述的常规互连结构相比在各种可靠性测试期间不会失败。 本发明的互连结构在通孔的底部具有位于层间介质层内的扭结界面。 具体地，本发明的互连结构包括：第一介电层，其具有嵌入在其表面内的至少一个金属互连; 位于所述第一介电层顶部的第二电介质层，其中所述第二电介质层具有至少一个具有上线区域和下通孔区域的孔，其中所述下通孔区域包括扭结界面; 位于所述至少一个孔的至少垂直壁上的至少一对衬垫; 以及填充所述至少一个孔的导电材料。

    Signal Detector with Calibration Circuit Arrangement
    106.
    发明申请
    Signal Detector with Calibration Circuit Arrangement 有权
    具有校准电路布置的信号检测器

    公开(公告)号：US20070271054A1

    公开(公告)日：2007-11-22

    申请号：US11383821

    申请日：2006-05-17

    申请人： Minhan Chen ,  Louis Hsu ,  Joseph Natonio ,  Karl D. Selander ,  Michael A. Sorna ,  Steven J. Zier

    发明人： Minhan Chen ,  Louis Hsu ,  Joseph Natonio ,  Karl D. Selander ,  Michael A. Sorna ,  Steven J. Zier

    IPC分类号： G06F19/00

    CPC分类号： H04L25/0274 ,  H04L25/0296

    摘要： A signal detector and method detect the presence or absence of an incoming differential signal. The method nullifies the DC off-set of the signal detector so that it can detect a signal within a very narrow window. The common mode levels of the signal and reference paths are used for calibration which is done automatically by use of an embedded algorithm residing in a digital block. The calibration range and resolution are predetermined to cope with the technology, modeling, design methodology and human error.

    摘要翻译： 信号检测器和方法检测输入差分信号的存在或不存在。 该方法使信号检测器的DC偏移无效，使得其可以在非常窄的窗口内检测信号。 信号和参考路径的共模电平用于通过使用位于数字块中的嵌入式算法自动完成的校准。 预定校准范围和分辨率，以应对技术，建模，设计方法和人为错误。

    SEMICONDUCTOR DEVICE STRUCTURES WITH REDUCED JUNCTION CAPACITANCE AND DRAIN INDUCED BARRIER LOWERING AND METHODS FOR FABRICATING SUCH DEVICE STRUCTURES AND FOR FABRICATING A SEMICONDUCTOR-ON-INSULATOR SUBSTRATE
    108.
    发明申请
    SEMICONDUCTOR DEVICE STRUCTURES WITH REDUCED JUNCTION CAPACITANCE AND DRAIN INDUCED BARRIER LOWERING AND METHODS FOR FABRICATING SUCH DEVICE STRUCTURES AND FOR FABRICATING A SEMICONDUCTOR-ON-INSULATOR SUBSTRATE 失效
    具有降低的接合电容和漏极诱发障碍物下降的半导体器件结构以及用于制造这种器件结构和用于制造半导体绝缘体衬底的方法

    公开(公告)号：US20070246752A1

    公开(公告)日：2007-10-25

    申请号：US11379655

    申请日：2006-04-21

    申请人： Kangguo Cheng ,  Louis Hsu ,  Jack Mandelman ,  Haining Yang

    发明人： Kangguo Cheng ,  Louis Hsu ,  Jack Mandelman ,  Haining Yang

    IPC分类号： H01L29/76

    CPC分类号： H01L29/66545 ,  H01L29/51 ,  H01L29/513 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78603 ,  Y10S438/96

    摘要： Semiconductor device structures with reduced junction capacitance and drain induced barrier lowering, methods for fabricating such device structures, and methods for forming a semiconductor-on-insulator substrate. The semiconductor structure comprises a semiconductor layer and a dielectric layer disposed between the semiconductor layer and the substrate. The dielectric layer includes a first dielectric region with a first dielectric constant and a second dielectric region with a second dielectric constant that is greater than the first dielectric constant. In one embodiment, the dielectric constant of the first dielectric region may be less than about 3.9 and the dielectric constant of the second dielectric region may be greater than about ten (10). The semiconductor-on-insulator substrate comprises a semiconductor layer separated from a bulk layer by an insulator layer of a high-dielectric constant material. The fabrication methods comprise modifying a region of the dielectric layer to have a lower dielectric constant.

    摘要翻译： 具有减小的结电容和漏极引起的屏障降低的半导体器件结构，用于制造这种器件结构的方法以及用于形成绝缘体上半导体衬底的方法。 半导体结构包括半导体层和设置在半导体层和衬底之间的电介质层。 电介质层包括具有第一介电常数的第一电介质区域和具有大于第一介电常数的第二介电常数的第二电介质区域。 在一个实施例中，第一电介质区域的介电常数可以小于约3.9，并且第二电介质区域的介电常数可以大于约十（10）。 绝缘体上半导体衬底包括通过高介电常数材料的绝缘体层与本体层分离的半导体层。 制造方法包括修改介电层的区域以具有较低的介电常数。

    INTEGRATED CIRCUIT CHIP WITH FETS HAVING MIXED BODY THICKNESSES AND METHOD OF MANUFACTURE THEREOF
    109.
    发明申请
    INTEGRATED CIRCUIT CHIP WITH FETS HAVING MIXED BODY THICKNESSES AND METHOD OF MANUFACTURE THEREOF 有权
    集成电路芯片与具有混合体积的FETs及其制造方法

    公开(公告)号：US20070235806A1

    公开(公告)日：2007-10-11

    申请号：US11279063

    申请日：2006-04-07

    申请人： Rajiv Joshi ,  Louis Hsu ,  Oleg Gluschenkov

    发明人： Rajiv Joshi ,  Louis Hsu ,  Oleg Gluschenkov

    IPC分类号： H01L27/12

    CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/78654

    摘要： An Integrated Circuit (IC) chip that may be a bulk CMOS IC chip with silicon on insulator (SOI) Field Effect Transistors (FETs) and method of making the chip. The IC chip includes areas with pockets of buried insulator strata and FETs formed on the strata are SOI FETs. The SOI FETs may include Partially Depleted SOI (PD-SOI) FETs and Fully Depleted SOI (FD-SOI) FETs and the chip may include bulk FETs as well. The FETs are formed by contouring the surface of a wafer, conformally implanting oxygen to a uniform depth, and planarizing to remove the Buried OXide (BOX) in bulk FET regions.

    摘要翻译： 一种集成电路（IC）芯片，其可以是具有绝缘体上硅（SOI）场效应晶体管（FET）和制造芯片的方法的体CMOS IC芯片。 IC芯片包括具有埋入绝缘体层的凹坑的区域，并且在层上形成的FET是SOI FET。 SOI FET可以包括部分耗尽的SOI（PD-SOI）FET和完全耗尽的SOI（FD-SOI）FET，并且芯片也可以包括体FET。 FET通过轮廓化晶片的表面，将氧气保形地均匀地注入到均匀的深度，并平坦化以去除体FET区域中的掩埋氧化物（BOX）来形成。

    BODY CAPACITOR FOR SOI MEMORY
    110.
    发明申请
    BODY CAPACITOR FOR SOI MEMORY 有权
    用于SOI存储器的身体电容器

    公开(公告)号：US20070202637A1

    公开(公告)日：2007-08-30

    申请号：US11742147

    申请日：2007-04-30

    申请人： Jack Mandelman ,  Louis Hsu ,  Rajiv Joshi

    发明人： Jack Mandelman ,  Louis Hsu ,  Rajiv Joshi

    IPC分类号： H01L21/84

    CPC分类号： H01L21/84 ,  H01L27/108 ,  H01L27/10832 ,  H01L27/10858 ,  H01L27/1203 ,  H01L29/94

    摘要： A semiconductor structure having a body capacitance plate, which is formed with a process that assures that the body capacitance plate is self-aligned to both the source line (SL) diffusion and the bitline diffusion is provided. Thus the amount of overlap between the SL and the bitline diffusions and the body capacitance plate is precisely controlled. More specifically, the present invention forms the structure of a 1T-capacitorless SOI body charge storage cell having sidewall capacitor plates using a process that assures that there is 1) minimal overlap between plate and source/drain diffusions, and 2) that the minimal overlap obtained in the present invention is precisely controlled and is not subject to alignment tolerances. The inventive cell results in larger signal margin, improved performance, smaller chip size, and reduced dynamic power dissipation relative to the prior art.

    摘要翻译： 提供一种具有体电容板的半导体结构，其形成有确保体电容板与源极线（SL）扩散和位线扩散两者自对准的工艺。 因此，SL和位线扩散和体电容板之间的重叠量被精确地控制。 更具体地说，本发明通过使用确保存在1）板和源极/漏极扩散之间的最小重叠的过程形成具有侧壁电容器板的1T无电容的SOI体电荷存储单元的结构，以及2）最小重叠 在本发明中获得的精确控制并且不受对准公差的影响。 与现有技术相比，本发明的电池产生更大的信号余量，改善的性能，更小的芯片尺寸和降低的动态功耗。