公开(公告)号：US20230307350A1

公开(公告)日：2023-09-28

申请号：US17701509

申请日：2022-03-22

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Indra V. Chary ,  Richard J. Hill

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/535 ,  H01L21/768

CPC classification number: H01L23/5221 ,  H01L23/5283 ,  H01L23/535 ,  H01L21/76816 ,  H01L21/76895

Abstract: A microelectronic device includes a stack structure having blocks separated by dielectric slot structures and each including a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. At least one of the blocks includes an upper stadium structure, two crest regions, a lower stadium structure, and two bridge regions. The upper stadium structure extends from and between two of the dielectric slot structures, and includes staircase structures having steps including edges of some of the tiers. The two crest regions are horizontally offset from the upper stadium structure. The lower stadium structure is below the upper stadium structure, is interposed between the two crest regions, and includes additional staircase structures. The two bridge regions are interposed between the lower stadium structure and the two of the dielectric slot structures, and extend between the two crest regions. Related memory devices, electronic systems, and methods are also described.

公开(公告)号：US11715685B2

公开(公告)日：2023-08-01

申请号：US17064453

申请日：2020-10-06

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Indra V. Chary ,  Nancy M. Lomeli ,  Xiao Li

IPC: H01L23/522 ,  G11C16/08 ,  G11C16/24 ,  H01L21/768 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H01L23/5226 ,  G11C16/08 ,  G11C16/24 ,  H01L21/76831 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A method of forming a microelectronic device includes forming a microelectronic device structure. The microelectronic device structure includes a stack structure comprising insulative structures and electrically conductive structures vertically alternating with the insulative structures, pillar structures extending vertically through the stack structure, an etch stop material vertically overlaying the stack structure, and a first dielectric material vertically overlying the etch stop material. The method further includes removing portions of the first dielectric material, the etch stop material, and an upper region of the stack structure to form a trench interposed between horizontally neighboring groups of the pillar structures, forming a liner material within the trench, and substantially filling a remaining portion of the trench with a second dielectric material to form a dielectric barrier structure.

公开(公告)号：US11705385B2

公开(公告)日：2023-07-18

申请号：US17367990

申请日：2021-07-06

Applicant: Micron Technology, Inc.

Inventor： Indra V. Chary ,  Chet E. Carter ,  Anilkumar Chandolu ,  Justin B. Dorhout ,  Jun Fang ,  Matthew J. King ,  Brett D. Lowe ,  Matthew Park ,  Justin D. Shepherdson

IPC: H01L23/48 ,  H01L21/311 ,  H01L21/033 ,  H01L21/768 ,  H01L21/28 ,  H10B43/10 ,  H10B43/27 ,  H10B41/10 ,  H10B41/27

CPC classification number: H01L23/481 ,  H01L21/0337 ,  H01L21/31111 ,  H01L21/76897 ,  H01L29/40117 ,  H10B43/10 ,  H10B43/27 ,  H10B41/10 ,  H10B41/27

Abstract: A method used in forming a memory array and conductive through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. A mask is formed comprising horizontally-elongated trench openings and operative TAV openings above the stack. Etching is conducted of unmasked portions of the stack through the trench and operative TAV openings in the mask to form horizontally-elongated trench openings in the stack and to form operative TAV openings in the stack. Conductive material is formed in the operative TAV openings in the stack to form individual operative TAVs in individual of the operative TAV openings in the stack. A wordline-intervening structure is formed in individual of the trench openings in the stack.

公开(公告)号：US20230117100A1

公开(公告)日：2023-04-20

申请号：US18083991

申请日：2022-12-19

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  Shawn D. Lyonsmith ,  Matthew J. King ,  Lise M. Clampitt ,  John Hopkins ,  Kevin Y. Titus ,  Indra V. Chary ,  Martin Jared Barclay ,  Anilkumar Chandolu ,  Pavithra Natarajan ,  Roger W. Lindsay

IPC: H10B43/27 ,  H01L23/528 ,  H10B43/10 ,  H01L23/522 ,  H01L21/02 ,  H10B51/20 ,  H01L21/67

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first deck located over a substrate, and a second deck located over the first deck, and pillars extending through the first and second decks. The first deck includes first memory cells, first control gates associated with the first memory cells, and first conductive paths coupled to the first control gates. The second conductive paths include second conductive pads located on a first level of the apparatus over the substrate. The second deck includes second memory cells, second control gates associated with the second memory cells, and second conductive paths coupled to the second control gates. The second conductive paths include second conductive pads located on a second level of the apparatus. The first and second conductive pads having lengths in a direction perpendicular to a direction from the first deck to the second deck.

公开(公告)号：US20230045353A1

公开(公告)日：2023-02-09

申请号：US17396939

申请日：2021-08-09

Applicant: Micron Technology, Inc.

Inventor： S M Istiaque Hossain ,  Indra V. Chary ,  Anilkumar Chandolu ,  Sidhartha Gupta ,  Shuangqiang Luo

IPC: H01L23/528 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11524 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: A microelectronic device, including a stack structure including alternating conductive structures and dielectric structures is disclosed. Memory pillars extend through the stack structure. Contacts are laterally adjacent to the memory pillars and extending through the stack structure. The contacts including active contacts and support contacts. The active contacts including a liner and a conductive material. The support contacts including the liner and a dielectric material. The conductive material of the active contacts is in electrical communication with the memory pillars. Methods and electronic systems are also disclosed.

公开(公告)号：US11563022B2

公开(公告)日：2023-01-24

申请号：US16550252

申请日：2019-08-25

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Indra V. Chary ,  Justin B. Dorhout ,  Jian Li ,  Haitao Liu ,  Paolo Tessariol

IPC: H01L29/76 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/1157

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. The operative channel-material strings in the laterally-spaced memory blocks comprise part of a memory plane. An elevationally-extending wall is in the memory plane laterally-between immediately-laterally-adjacent of the memory blocks and that completely encircles an island that is laterally-between immediately-laterally-adjacent of the memory blocks in the memory plane. Other embodiments, including method are disclosed.

公开(公告)号：US20220406712A1

公开(公告)日：2022-12-22

申请号：US17349158

申请日：2021-06-16

Applicant: Micron Technology, Inc.

Inventor： Indra V. Chary ,  Shuangqiang Luo ,  Lifang Xu

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573

Abstract: A microelectronic device comprises a stack structure, contact structures, and additional contact structures. The stack structure comprises a vertically alternating sequence of conductive material and insulative material arranged in tiers. The stack structure is divided into blocks each comprising a stadium structure including steps comprising horizontal ends of the tiers. The contact structures are within a horizontal area of the stadium structure and vertically extend through the stack structure. The additional contact structures are on at least some of the steps of the stadium structure and are coupled to the contact structures. Memory devices and electronic devices are also disclosed.

公开(公告)号：US11532638B2

公开(公告)日：2022-12-20

申请号：US17008130

申请日：2020-08-31

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  Shawn D. Lyonsmith ,  Matthew J. King ,  Lisa M. Clampitt ,  John Hopkins ,  Kevin Y. Titus ,  Indra V. Chary ,  Martin Jared Barclay ,  Anilkumar Chandolu ,  Pavithra Natarajan ,  Roger W. Lindsay

IPC: H01L27/11582 ,  H01L23/528 ,  H01L27/11565 ,  H01L23/522 ,  H01L27/11597 ,  H01L21/02 ,  H01L21/67 ,  G11C16/04

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first deck located over a substrate, and a second deck located over the first deck, and pillars extending through the first and second decks. The first deck includes first memory cells, first control gates associated with the first memory cells, and first conductive paths coupled to the first control gates. The second conductive paths include second conductive pads located on a first level of the apparatus over the substrate. The second deck includes second memory cells, second control gates associated with the second memory cells, and second conductive paths coupled to the second control gates. The second conductive paths include second conductive pads located on a second level of the apparatus. The first and second conductive pads having lengths in a direction perpendicular to a direction from the first deck to the second deck.

公开(公告)号：US20220336278A1

公开(公告)日：2022-10-20

申请号：US17231895

申请日：2021-04-15

Applicant: Micron Technology, Inc.

Inventor： Anilkumar Chandolu ,  Indra V. Chary

IPC: H01L21/768 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11582

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. The memory-block regions comprise part of a memory-plane region. A pair of elevationally-extending walls are formed that are laterally-spaced relative one another and that are individually horizontally-longitudinally-elongated. The pair of walls are one of (a) or (b), where: (a): in the memory-plane region laterally-between immediately-laterally-adjacent of the memory-block regions; and (b): in a region that is edge-of-plane relative to the memory-plane region. Through the horizontally-elongated trenches and after forming the pair of walls, sacrificial material that is in the first tiers is isotropically etching away and replaced with conducting material of individual conducting lines. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US11444099B2

公开(公告)日：2022-09-13

申请号：US16922792

申请日：2020-07-07

Applicant: Micron Technology, Inc.

Inventor： Anilkumar Chandolu ,  Indra V. Chary

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11524

Abstract: Microelectronic devices include a stack structure with a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. Conductive contact structures extend through the stack structure. An insulative material is between the conductive contact structures and the tiers of the stack structure. In a lower tier portion of the stack structure, a conductive structure, of the conductive structures, has a portion extending a first width between a pair of the conductive contact structures. In a portion of the stack structure above the lower tier portion, an additional conductive structure, of the conductive structures, has an additional portion extending a second width between the pair of the conductive contact structures. The second width is greater than the first width. Related methods and electronic systems are also disclosed.