公开(公告)号：US10886213B2

公开(公告)日：2021-01-05

申请号：US16984710

申请日：2020-08-04

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Teruhiro Kuwajima ,  Yasutaka Nakashiba ,  Akira Matsumoto ,  Akio Ono ,  Tetsuya Iida

IPC: H03L7/06 ,  H01L23/522 ,  H01L49/02 ,  H03L7/099 ,  H01L29/93 ,  H01L27/06

Abstract: A semiconductor device has a coil and wirings under the coil. In addition, a distance between the upper face of the wirings and the bottom face of the coil is 7 μm or larger, and the wirings have a plurality of linear wiring parts each wiring width of which is 1 μm or smaller. In addition, the linear wiring parts do not configure a loop wiring, and the coil and the linear wiring parts are overlapped with each other in planar view.

公开(公告)号：US10656442B2

公开(公告)日：2020-05-19

申请号：US15976912

申请日：2018-05-11

Applicant: Renesas Electronics Corporation

Inventor： Tetsuya Iida ,  Yasutaka Nakashiba ,  Shinichi Kuwabara

IPC: G02F1/01 ,  G02F1/025

Abstract: In an optical waveguide supplied with electricity by using a heater, miniaturization of the device is achieved by enhancing heat dissipation efficiency and heat resistance. In a modulator including an optical waveguide formed on an insulating film, a first interlayer insulating film that covers the optical waveguide, a heater formed on the first interlayer insulating film, and a second interlayer insulating film that covers the heater, a heat conducting portion adjacent to the optical waveguide and the heater and penetrating the first and second interlayer insulating films is formed.

公开(公告)号：US10459162B2

公开(公告)日：2019-10-29

申请号：US16036455

申请日：2018-07-16

Applicant: Renesas Electronics Corporation

Inventor： Tetsuya Iida ,  Yasutaka Nakashiba

IPC: G02B6/122 ,  G02B6/125 ,  G02B6/12

Abstract: To provide a semiconductor device including a low-loss optical waveguide. The optical waveguide included in the semiconductor device has a core layer covered with first and second clad layers having respectively different refractive indices. A portion of the core layer is covered at a first ratio, that is, a ratio of the first clad layer to the second clad layer and at the same time, a second ratio, that is, a ratio of the second clad layer to the first clad layer. At this time, the first ratio and the second ratio are each a finite value more than 0.

公开(公告)号：US10418321B2

公开(公告)日：2019-09-17

申请号：US15954213

申请日：2018-04-16

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinichi Kuwabara ,  Tetsuya Iida ,  Yasutaka Nakashiba

IPC: H01L23/522 ,  H01L23/31 ,  H01L23/528 ,  H01L23/64 ,  H01L23/552 ,  H01L21/8238 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L23/495 ,  H01L23/532 ,  H01L21/265

Abstract: A compact semiconductor device with an isolator. The semiconductor device includes two chips, namely a first semiconductor chip and a second semiconductor chip which are stacked with the main surfaces of the semiconductor chips partially facing each other. A first coil and a second coil which are formed in the first semiconductor chip and the second semiconductor chip respectively are arranged to face each other so as to be magnetically coupled during operation of the semiconductor device. The pair of first and second coils make up an isolator. The first coil is arranged in a manner to overlap part of the circuit region of the first semiconductor chip in plan view and the second coil is arranged in a manner to overlap part of the circuit region of the second semiconductor chip in plan view.

公开(公告)号：US09978512B2

公开(公告)日：2018-05-22

申请号：US15346918

申请日：2016-11-09

Applicant: Renesas Electronics Corporation

Inventor： Masaya Kawano ,  Yasutaka Nakashiba

IPC: H01F38/14 ,  H01F27/28 ,  H01F27/40 ,  H01L23/535 ,  H01L27/12 ,  H01L49/02 ,  H01L29/06 ,  H01F17/00

CPC classification number: H01F38/14 ,  H01F17/0013 ,  H01F27/2804 ,  H01F27/40 ,  H01F2017/0086 ,  H01F2027/2809 ,  H01F2038/143 ,  H01L23/535 ,  H01L27/1203 ,  H01L28/10 ,  H01L29/0649 ,  H01L2224/4813 ,  H01L2224/48137 ,  H01L2924/00014 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A circuit device, includes a semiconductor substrate, and a first inductor provided over said semiconductor substrate, and a first interconnect provided over said semiconductor substrate and coupled with first inductor.

公开(公告)号：US09899446B2

公开(公告)日：2018-02-20

申请号：US15372775

申请日：2016-12-08

Applicant: Renesas Electronics Corporation

Inventor： Tetsuya Iida ,  Yasutaka Nakashiba

IPC: H01L27/14 ,  H01L27/146

CPC classification number: H01L27/14643 ,  H01L27/14607 ,  H01L27/1461 ,  H01L27/14614

Abstract: A solid-state image sensing device capable of suppressing a dark current and transfer failure during a global shutter operation is provided. The solid-state image sensing device according to one embodiment includes: a semiconductor substrate having a main surface and a back surface being on the opposite side of the main surface; a well region arranged in contact with the main surface in the semiconductor substrate; a photoelectric conversion region arranged in contact with the main surface in the well region; a charge holding region arranged in contact with the main surface in the well region; a floating diffusion region arranged in contact with the main surface in the well region; a first transfer gate so formed as to face the well region and the charge holding region; and a second transfer gate so formed as to face the well region.

公开(公告)号：US09846831B2

公开(公告)日：2017-12-19

申请号：US15080261

申请日：2016-03-24

Applicant: Renesas Electronics Corporation

Inventor： Yasutaka Nakashiba ,  Hiroaki Ohkubo ,  Mitsuji Okada ,  Shigeharu Nakata ,  Shuuichi Kagawa

IPC: G06K19/06 ,  G06K19/073 ,  G11C7/24 ,  H03K19/0175

CPC classification number: G06K19/073 ,  G11C7/24 ,  H03K19/017509

Abstract: A memory card includes a memory that stores data, a driver that transmits the data received from the memory, and at least one transmitter that transmits the data received from the driver to a receiver provided in an external main unit. The driver and the transmitter are provided in a single IC (Integrated Circuit) chip and are not overlapped with each other in planar view, and the transmitter includes a coil.

公开(公告)号：US09666659B2

公开(公告)日：2017-05-30

申请号：US14203037

申请日：2014-03-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasutaka Nakashiba ,  Kenta Ogawa

IPC: H01L49/02 ,  G11C5/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L23/522 ,  H01L23/00 ,  H05K3/00 ,  H01L23/48 ,  H01L27/06 ,  H05K1/11 ,  H05K3/28

CPC classification number: H01L28/10 ,  G11C5/005 ,  H01L21/561 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/48 ,  H01L23/49855 ,  H01L23/5227 ,  H01L23/562 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L27/0688 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/15183 ,  H01L2924/181 ,  H01L2924/1815 ,  H05K1/117 ,  H05K3/0052 ,  H05K3/284 ,  H05K2201/0949 ,  H05K2201/09845 ,  H05K2203/0228 ,  H05K2203/1316 ,  H05K2203/1572 ,  Y10T29/4902 ,  Y10T29/4913 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An external storage device including an interconnect substrate having a contact type external terminal, at least one semiconductor chip disposed over a first surface of the interconnect substrate, and a sealing resin layer which seals the at least one semiconductor chip and does not cover the external terminal. The at least one semiconductor chip includes a storage device, an inductor being connected to the storage device, a driver circuit configured to control the inductor and an interconnect layer. The interconnect layer is formed at a first surface of the semiconductor chip and includes the inductor. The first surface of the semiconductor chip is other than facing the first surface of the interconnect substrate, and the inductor and the driver circuit are connected to each other through the interconnect layer.

公开(公告)号：US09502175B2

公开(公告)日：2016-11-22

申请号：US14339414

申请日：2014-07-23

Applicant: Renesas Electronics Corporation

Inventor： Masaya Kawano ,  Yasutaka Nakashiba

IPC: H05K1/16 ,  H01F38/14 ,  H01F17/00

CPC classification number: H01F38/14 ,  H01F17/0013 ,  H01F27/2804 ,  H01F27/40 ,  H01F2017/0086 ,  H01F2027/2809 ,  H01F2038/143 ,  H01L23/535 ,  H01L27/1203 ,  H01L28/10 ,  H01L29/0649 ,  H01L2224/4813 ,  H01L2224/48137 ,  H01L2924/00014 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A circuit device includes a semiconductor substrate, a first inductor provided over the semiconductor substrate, and a second inductor provided over the semiconductor substrate and coupled to the first inductor. The first inductor and second inductor are wound in a same direction with each other from respective inner end portions to respective outer end portions thereof.

Abstract translation: 电路装置包括半导体衬底，设置在半导体衬底上的第一电感器和设置在半导体衬底上并耦合到第一电感器的第二电感器。 第一电感器和第二电感器从相应的内端部到相应的外端部彼此以相同方向缠绕。

公开(公告)号：US09355998B2

公开(公告)日：2016-05-31

申请号：US14518024

申请日：2014-10-20

Applicant: Renesas Electronics Corporation

Inventor： Yasutaka Nakashiba

IPC: H01L27/08 ,  H01L25/065 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01F17/00 ,  H01F38/14

CPC classification number: H01L25/0655 ,  H01F17/0013 ,  H01F38/14 ,  H01L23/48 ,  H01L23/5227 ,  H01L23/528 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/157 ,  H01L2924/19042 ,  H01L2924/19104 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: In a semiconductor device, a first semiconductor chip includes a first circuit and a first inductor, and a second semiconductor chip includes a second circuit and chip-side connecting terminals. An interconnect substrate is placed over the first semiconductor chip and the second semiconductor chip. The interconnect substrate includes a second inductor and substrate-side connecting terminals. The second inductor is located above the first inductor. The chip-side connecting terminals and the two substrate-side connecting terminals are connected through first solder balls.

Abstract translation: 在半导体器件中，第一半导体芯片包括第一电路和第一电感器，第二半导体芯片包括第二电路和芯片侧连接端子。 互连基板被放置在第一半导体芯片和第二半导体芯片上。 互连基板包括第二电感器和衬底侧连接端子。 第二电感器位于第一电感器的上方。 芯片侧连接端子和两个基板侧连接端子通过第一焊球连接。