公开(公告)号：US20170371740A1

公开(公告)日：2017-12-28

申请号：US15646025

申请日：2017-07-10

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brent Haukness

IPC: G06F11/10 ,  G06F12/02 ,  G11C29/52

Abstract: A memory device is disclosed that includes a row of storage locations that form plural columns. The plural columns include data columns to store data and a tag column to store tag information associated with error locations in the data columns. Each data column is associated with an error correction location including an error code bit location. Logic retrieves and stores the tag information associated with the row in response to activation of the row. A bit error in an accessed data column is repaired by a spare bit location based on the tag information.

公开(公告)号：US09824779B2

公开(公告)日：2017-11-21

申请号：US14717048

申请日：2015-05-20

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Vlad Fruchter ,  Chi-Ming Yeung

IPC: G11C29/00 ,  G11C29/56 ,  G06F11/07 ,  G06F3/06 ,  G11C29/44 ,  G06F11/10 ,  G11C29/52 ,  G11C5/04 ,  G11C11/401

CPC classification number: G11C29/765 ,  G06F3/0629 ,  G06F11/0751 ,  G06F11/1008 ,  G11C5/04 ,  G11C11/401 ,  G11C29/44 ,  G11C29/4401 ,  G11C29/52 ,  G11C29/56008 ,  G11C29/88 ,  G11C2029/4402

Abstract: In response to a first memory access transaction having a first base address, data fields and a repair fields are retrieved from a first DRAM channel. The data fields include a first data field. The repair fields include a first repair field storing repair data. The repair data is to replace any data in the first data field. In response to a second memory access transaction having a second base address, repair tag fields are retrieved from a second DRAM channel. The repair tag fields include a repair tag field that indicates the repair data is be replace the data stored in the first data field.

公开(公告)号：US20170330610A1

公开(公告)日：2017-11-16

申请号：US15483817

申请日：2017-04-10

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Suresh Rajan ,  Scott C. Best

IPC: G11C11/408 ,  G11C7/10 ,  G06F13/16 ,  G06F12/06 ,  G11C5/04 ,  G11C11/4093 ,  G11C11/4076 ,  G11C7/22

Abstract: The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of the memory system in different configurations.

公开(公告)号：US20170315935A1

公开(公告)日：2017-11-02

申请号：US15485115

申请日：2017-04-11

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Frederick A. Ware

IPC: G06F12/14 ,  G06F13/16 ,  G06F12/02

CPC classification number: G06F12/1458 ,  G06F3/0619 ,  G06F12/023 ,  G06F13/16 ,  G06F13/1657 ,  G06F13/1684 ,  G06F13/1694 ,  G06F2212/1044 ,  G06F2212/1052

Abstract: A multi-rank memory system in which calibration operations are performed between a memory controller and one rank of memory while data is transferred between the controller and other ranks of memory. A memory controller performs a calibration operation that calibrates parameters pertaining to transmission of data via a first data bus between the memory controller and a memory device in a first rank of memory. While the controller performs the calibration operation, the controller also transfers data with a memory device in a second rank of memory via a second data bus.

公开(公告)号：US09753521B2

公开(公告)日：2017-09-05

申请号：US14951150

申请日：2015-11-24

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Robert E. Palmer ,  John W. Poulton ,  Andrew M. Fuller

IPC: G06F1/04 ,  G06F1/08 ,  G06F1/32 ,  G11C7/04 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G06F13/16 ,  G06F1/12 ,  G06F3/06 ,  G06F9/38 ,  G06F12/0855 ,  G06F13/36

CPC classification number: G06F1/3237 ,  G06F1/12 ,  G06F1/3225 ,  G06F1/324 ,  G06F3/0604 ,  G06F3/0625 ,  G06F3/0629 ,  G06F3/0673 ,  G06F9/3836 ,  G06F12/0857 ,  G06F13/1689 ,  G06F13/36 ,  G06F2201/88 ,  G11C7/04 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2207/2254 ,  Y02D10/14

Abstract: In an integrated circuit device that outputs data values during respective transmit intervals defined by transitions of a transmit clock, the phase of the transmit clock is shifted by half a transmit interval to enable a timing calibration operation. Thereafter, a sequence of data values is transmitted to another integrated circuit device in response to the phase-shifted transmit clock and a samples of the sequence of data values are received from the other integrated circuit device. The received samples are compared with the sequence of data values to determine a phase update value, including comparing at least one received sample with two adjacent data values within the sequence of data values, and the phase of the transmit clock is incrementally advanced or retarded according to the phase update value.

公开(公告)号：US09721642B2

公开(公告)日：2017-08-01

申请号：US15155794

申请日：2016-05-16

Applicant: Rambus Inc.

Inventor： Craig E. Hampel ,  Richard E. Perego ,  Stefanos Sidiropoulos ,  Ely K. Tsern ,  Frederick A. Ware

IPC: G11C11/4076 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4078 ,  G06F12/02 ,  G11C11/406 ,  G11C21/00 ,  G06F3/06 ,  G11C11/4072 ,  G11C11/4093 ,  H04L7/00

CPC classification number: G11C11/4076 ,  G06F3/061 ,  G06F3/0629 ,  G06F3/0671 ,  G06F12/0246 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222 ,  G11C11/40611 ,  G11C11/4072 ,  G11C11/4078 ,  G11C11/4093 ,  G11C21/00 ,  G11C2207/2254 ,  H04L7/0025 ,  H04L7/0079 ,  H04L7/0091

Abstract: A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration.

公开(公告)号：US20170177487A1

公开(公告)日：2017-06-22

申请号：US15376507

申请日：2016-12-12

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brent Haukness

IPC: G06F12/0888

CPC classification number: G06F13/1689

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory controller is disclosed. The memory controller includes write queue logic that has first storage to temporarily store signal components of a write operation. The signal components include an address and write data. A transfer interface issues the signal components of the write operation to a bank of a storage class memory (SCM) device and generates a time value. The time value represents a minimum time interval after which a subsequent write operation can be issued to the bank. The write queue logic includes an issue queue to store the address and the time value for a duration corresponding to the time value.

公开(公告)号：US20170162252A1

公开(公告)日：2017-06-08

申请号：US15352366

申请日：2016-11-15

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Thomas Vogelsang

IPC: G11C11/4093 ,  G11C11/4076 ,  G11C11/4094

CPC classification number: G11C11/4093 ,  G11C11/4076 ,  G11C11/4094 ,  G11C11/4097

Abstract: A memory stack comprises at least two memory components. The memory components have a first data link interface and are to transmit signals on a data link coupled to the first data link interface at a first voltage level. A buffer component has a second data link interface coupled to the data link. The buffer component is to receive signals on the second data link interface at the first voltage level. A level shifting latch produces a second voltage level in response to receiving the signals at the second data link interface, where the second voltage level is higher than the first voltage level.

公开(公告)号：US20170147421A1

公开(公告)日：2017-05-25

申请号：US15341959

申请日：2016-11-02

Applicant: Rambus Inc.

Inventor： Yuanlong Wang ,  Frederick A. Ware

IPC: G06F11/07 ,  H03M13/09 ,  H03M13/00 ,  G06F11/10

CPC classification number: G06F11/0727 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/076 ,  G06F11/0793 ,  G06F11/10 ,  G06F11/1004 ,  G06F11/1008 ,  G06F11/1044 ,  G06F11/1068 ,  G06F11/1402 ,  G06F13/4286 ,  H03M13/09 ,  H03M13/29 ,  H03M13/2906 ,  H03M13/611 ,  H04L1/0003 ,  H04L1/0008 ,  H04L1/0061 ,  H04L1/08 ,  H04L1/1867 ,  H04L2001/0093

Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.

公开(公告)号：US20170132150A1

公开(公告)日：2017-05-11

申请号：US15295723

申请日：2016-10-17

Applicant: Rambus Inc.

Inventor： Craig E. Hampel ,  Frederick A. Ware

IPC: G06F12/1081 ,  G06F13/16 ,  G06F13/28

CPC classification number: G06F13/1642 ,  G06F12/1081 ,  G06F13/1663 ,  G06F13/1678 ,  G06F13/1684 ,  G06F13/28 ,  G06F13/4243 ,  G06F2212/656 ,  G11C5/04 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1075 ,  H05K1/181 ,  H05K2201/09227 ,  H05K2201/10159 ,  Y02D10/14 ,  Y02D10/151 ,  Y02P70/611

Abstract: A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands.