公开(公告)号：US20150318169A1

公开(公告)日：2015-11-05

申请号：US14267634

申请日：2014-05-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Ajey Poovannummoottil Jacob ,  Jody A. Fronheiser ,  Murat Kerem Akarvardar ,  David Paul Brunco

IPC: H01L21/02 ,  H01L29/161 ,  H01L29/66

CPC classification number: H01L29/161 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7848

Abstract: One illustrative method disclosed herein includes, among other things, forming a fin in a semiconductor substrate and performing an epitaxial deposition process using a combination of silane (SiH4), dichlorosilane (SiH2Cl2), germane (GeH4) and a carrier gas to form an epi semiconductor material around the fin, wherein the flow rate of dichlorosilane used during the epitaxial deposition process is equal to 10-90% of the combined flow rate of silane and dichlorosilane.

Abstract translation: 本文公开的一种说明性方法包括在半导体衬底中形成翅片并使用硅烷（SiH 4），二氯硅烷（SiH 2 Cl 2），锗烷（GeH 4）和载气的组合进行外延沉积工艺以形成外延 散热片周围的半导体材料，其中在外延沉积工艺期间使用的二氯硅烷的流速等于硅烷和二氯硅烷的组合流速的10-90％。

公开(公告)号：US20150279973A1

公开(公告)日：2015-10-01

申请号：US14242472

申请日：2014-04-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Murat Kerem Akarvardar ,  Jody A. Fronheiser ,  Ajey Poovannummoottil Jacob

IPC: H01L29/66 ,  H01L29/10 ,  H01L21/84

CPC classification number: H01L29/66795 ,  H01L29/1054

Abstract: One illustrative method disclosed herein includes, among other things, performing an epitaxial deposition process to form an epi SiGe layer above a recessed layer of insulating material and on an exposed portion of a fin, wherein the concentration of germanium in the layer of epi silicon-germanium (SixGe1-x) is equal to or greater than a target concentration of germanium for the final fin, performing a thermal anneal process in an inert processing environment to cause germanium in the epi SiGe to diffuse into the fin and thereby define an SiGe region in the fin, after performing the thermal anneal process, performing at least one process operation to remove the epi SiGe and, after removing the epi SiGe, forming a gate structure around at least a portion of the SiGe region.

Abstract translation: 本文公开的一种说明性方法包括进行外延沉积工艺以在绝缘材料的凹陷层上方和鳍的暴露部分上形成外延SiGe层，其中外延硅 - 锗（SixGe1-x）等于或大于用于最终翅片的锗的目标浓度，在惰性处理环境中进行热退火工艺以使外延SiGe中的锗扩散到翅片中，从而限定SiGe区域 在翅片中，在进行热退火处理之后，进行至少一个处理操作以去除外延SiGe，并且在去除外延SiGe之后，在SiGe区域的至少一部分周围形成栅极结构。

公开(公告)号：US20150255555A1

公开(公告)日：2015-09-10

申请号：US14197686

申请日：2014-03-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Ajey Poovannummoottil Jacob ,  Michael Hargrove ,  William J. Taylor, Jr.

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L29/1054 ,  H01L29/785

Abstract: One illustrative method disclosed herein involves, among other things, forming a first epi semiconductor material on the exposed opposite sidewalls of a fin to thereby define a semiconductor body, performing at least one etching process to remove at least a portion of the substrate portion of the fin positioned between the first epi semiconductor materials positioned on the opposite sidewalls of the fin and to thereby define a back-gate cavity, forming a back-gate insulating material within the back-gate cavity and on the first epi semiconductor materials, forming a back-gate electrode on the back-gate insulation material within the back-gate cavity and forming a gate structure comprised of a gate insulation layer and a gate electrode around the semiconductor bodies.

Abstract translation: 本文公开的一种说明性方法除其他外包括在鳍的暴露的相对侧壁上形成第一外延半导体材料，从而限定半导体本体，执行至少一个蚀刻工艺以去除衬底部分的至少一部分 翅片定位在位于翅片的相对侧壁上的第一外延半导体材料之间，从而限定背栅腔，在背栅腔内和第一外延半导体材料上形成背栅绝缘材料，形成背 在后栅极腔内的背栅极绝缘材料上形成栅极电极，并且形成由半导体本体周围的栅极绝缘层和栅极电极构成的栅极结构。

公开(公告)号：US20150228792A1

公开(公告)日：2015-08-13

申请号：US14175113

申请日：2014-02-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Ruilong Xie ,  Michael Hargrove

IPC: H01L29/78 ,  H01L21/306 ,  H01L29/51 ,  H01L21/02 ,  H01L29/16 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/51 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/778

Abstract: One device disclosed includes a gate structure positioned around a perimeter surface of the fin, a layer of channel semiconductor material having an axial length in the channel length direction of the device that corresponds approximately to the overall width of the gate structure being positioned between the gate structure and around the outer perimeter surface of the fin, wherein an inner surface of the layer of channel semiconductor material is spaced apart from and does not contact the outer perimeter surface of the fin. One method disclosed involves, among other things, forming first and second layers of semiconductor material around the fin, forming a gate structure around the second semiconductor material, removing the portions of the first and second layers of semiconductor material positioned laterally outside of sidewall spacers and removing the first layer of semiconductor material positioned below the second layer of semiconductor material.

Abstract translation: 所公开的一种装置包括围绕翅片的周边表面定位的栅极结构，沟道半导体材料层，其在器件的沟道长度方向上具有轴向长度，其大致对应于位于栅极之间的栅极结构的总宽度 结构并且围绕翅片的外周表面周围，其中沟道半导体材料层的内表面与翅片的外周表面间隔开并且不接触鳍的外周表面。 公开的一种方法尤其涉及在翅片周围形成第一和第二层半导体材料，围绕第二半导体材料形成栅极结构，去除位于侧壁间隔横向外侧的第一和第二半导体层的部分，以及 去除位于第二半导体材料层下方的第一半导体材料层。

公开(公告)号：US20150187905A1

公开(公告)日：2015-07-02

申请号：US14143468

申请日：2013-12-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiuyu Cai ,  Ajey Poovannummoottil Jacob ,  Daniel T. Pham ,  Mark V. Raymond ,  Christopher M. Prindle ,  Catherine B. Labelle ,  Linus Jang ,  Robert Teagle

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/51 ,  H01L29/423 ,  H01L21/768 ,  H01L21/3105 ,  H01L29/417

CPC classification number: H01L29/6681 ,  H01L21/31055 ,  H01L21/76897 ,  H01L29/0692 ,  H01L29/4175 ,  H01L29/41791 ,  H01L29/42364 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7843 ,  H01L29/785 ,  H01L29/7851

Abstract: One method disclosed herein includes, among other things, forming sidewall spacers adjacent opposite sides of a sacrificial gate electrode of a sacrificial gate structure, forming a tensile-stressed layer of insulating material adjacent the sidewall spacers, removing the sacrificial gate structure to define a replacement gate cavity positioned between the sidewall spacers, forming a replacement gate structure in the replacement gate cavity, forming a tensile-stressed gate cap layer above the replacement gate structure and within the replacement gate cavity and, after forming the tensile-stressed gate cap layer, removing the tensile-stressed layer of insulating material.

Abstract translation: 本文公开的一种方法尤其包括邻近牺牲栅极结构的牺牲栅电极的相对侧的侧壁间隔壁，形成邻近侧壁间隔物的绝缘材料的拉应力层，去除牺牲栅极结构以限定替换 门腔定位在侧壁间隔件之间，在置换栅腔中形成替换栅极结构，在置换栅极结构之上和置换栅极腔内形成拉伸应力栅极盖层，并且在形成拉伸应力栅极盖层之后， 去除绝缘材料的拉应力层。

公开(公告)号：US20150014776A1

公开(公告)日：2015-01-15

申请号：US13937939

申请日：2013-07-09

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Murat Kerem Akarvardar ,  Xiuyu Cai ,  Ajey Poovannummoottil Jacob

IPC: H01L21/8234 ,  H01L29/78 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/76208 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/0653

Abstract: A fin field effect transistor integrated circuit (FinFET IC) has a plurality of fins extending from a semiconductor substrate, where a trough is defined between adjacent fins. A second dielectric is positioned within the trough, and a protruding portion of the fins extends above the second dielectric. A first dielectric is positioned between the fin sidewalls and the second dielectric.

Abstract translation: 翅片场效应晶体管集成电路（FinFET IC）具有从半导体衬底延伸的多个鳍，其中在相邻鳍之间限定有槽。 第二电介质位于槽内，并且翅片的突出部分在第二电介质上方延伸。 第一电介质位于翅片侧壁和第二电介质之间。

公开(公告)号：US20210063655A1

公开(公告)日：2021-03-04

申请号：US16559979

申请日：2019-09-04

Applicant: GLOBALFOUNDRIES Inc. ,  KHALIFA UNIVERSITY OF SCIENCE AND TECHNOLOGY

Inventor： Sujith Chandran ,  Marcus Dahlem ,  Ajey Poovannummoottil Jacob ,  Yusheng Bian ,  Bruna Paredes ,  Jaime Viegas

IPC: G02B6/42 ,  G02B6/293

Abstract: Structures for a wavelength-division multiplexing filter and methods of fabricating a structure for a wavelength-division multiplexing filter. The structure includes a first waveguide core, a second waveguide core laterally spaced from the first waveguide core, and a ring resonator arranged in a vertical direction over the first waveguide core and the second waveguide core. The ring resonator is also arranged in a lateral direction between the first waveguide core and the second waveguide core. The first and second waveguide cores are composed of a semiconductor material, such as single-crystal silicon, and the ring resonator is composed of a dielectric material, such as silicon nitride.

公开(公告)号：US20210055478A1

公开(公告)日：2021-02-25

申请号：US16549197

申请日：2019-08-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yusheng Bian ,  Ajey Poovannummoottil Jacob

IPC: G02B6/122 ,  G02B6/30 ,  G02B6/136

Abstract: Structures for a waveguide coupler and methods of fabricating a structure for a waveguide coupler. A first waveguide core has a first width, a second waveguide core has a second width less than the first width, and a waveguide coupler includes first and second tapers that are positioned between the first waveguide core and the second waveguide core. The second taper is directly connected with the first taper, and the first and second tapers connect the first and second waveguide cores.

公开(公告)号：US10818807B2

公开(公告)日：2020-10-27

申请号：US16253191

申请日：2019-01-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ajey Poovannummoottil Jacob ,  Theodore J. Letavic ,  Abu Thomas ,  Yusheng Bian

IPC: H01L31/02 ,  H01L31/18 ,  G02B1/11 ,  G02B5/08 ,  H01L31/0232 ,  H01L31/0216 ,  G02B1/113

Abstract: The present disclosure generally relates to semiconductor detectors for use in optoelectronic devices and integrated circuit (IC) chips, and methods for forming same. More particularly, the present disclosure relates to integration of semiconductor detectors with Bragg reflectors. The photodetector of the present disclosure includes a substrate, a Bragg reflector disposed on the substrate, and a semiconductor detector disposed on the Bragg reflector. The Bragg reflector includes alternating layers of a semiconductor material and a dielectric material.

公开(公告)号：US10816727B1

公开(公告)日：2020-10-27

申请号：US16441678

申请日：2019-06-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yusheng Bian ,  Ajey Poovannummoottil Jacob

IPC: G02B6/125 ,  G02B6/136 ,  G02B6/12

Abstract: Structures for a waveguide bend and methods of fabricating a structure for a waveguide bend. A waveguide core has a first section, a second section, and a waveguide bend connecting the first section with the second section. The waveguide core includes a first side surface and a second side surface, the first side surface extends about an inner radius of the waveguide bend, and the second side surface extends about an outer radius of the waveguide bend. The waveguide bend includes a central region and a side region that is arranged adjacent to the central region at the first side surface or the second side surface. The central region has a first thickness, and the side region has a second thickness that is less than the first thickness.