公开(公告)号：US10673431B2

公开(公告)日：2020-06-02

申请号：US16161533

申请日：2018-10-16

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Jimmy Fort ,  Nicolas Borrel ,  Francesco La Rosa

IPC: H03K17/22 ,  G01R19/165 ,  G05F3/26 ,  G06F1/28 ,  H03K5/24 ,  G06F1/30 ,  G06F1/24

Abstract: A power supply voltage is monitored by a monitoring circuit including a variable current generator and a band gap voltage generator core receiving the variable current and including a first node and a second node. A control circuit connected to the first and second nodes is configured to deliver a control signal on a first output node having a first state when an increasing power supply voltage is below a first threshold and having a second state when increasing power supply voltage exceeds the first threshold. The first threshold is at least equal to the band gap voltage. An equalization circuit also connected to the first and second nodes with feedback to the variable current generator generates the bandgap voltage at a second output node. The control signal operates to control actuation of the equalization circuit.

公开(公告)号：US20190035450A1

公开(公告)日：2019-01-31

申请号：US16151388

申请日：2018-10-04

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Antonino Conte ,  Enrico Castaldo ,  Raul Andres Bianchi ,  Francesco La Rosa

IPC: G11C11/24 ,  G04F10/10

Abstract: A reading circuit for a charge-retention circuit stage is provided with a storage capacitor coupled between a first biasing terminal and a floating node, and a discharge element coupled between the floating node and a reference terminal. The reading circuit further has an operational amplifier having a first input terminal that is coupled to the floating node and receives a reading voltage, a second input terminal receives a reference voltage, and an output terminal on which it supplies an output voltage, the value of which is a function of the comparison between the reading voltage and the reference voltage and indicative of a residual charge in the storage capacitor. A shifting stage shifts the value of the reading voltage of the floating node, before the comparison is made between the reading voltage and the reference voltage for supplying the output voltage.

公开(公告)号：US10192999B2

公开(公告)日：2019-01-29

申请号：US15852826

申请日：2017-12-22

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Marc Mantelli ,  Stephan Niel ,  Arnaud Regnier ,  Francesco La Rosa ,  Julien Delalleau

IPC: H01L29/788 ,  G11C16/04 ,  H01L27/115 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L27/11553 ,  G11C16/14 ,  H01L21/266 ,  H01L21/306 ,  H01L21/308 ,  H01L21/3213 ,  H01L27/11524 ,  H01L27/11521 ,  H01L27/11556

Abstract: Various embodiments provide a memory cell that includes a vertical selection gate, a floating gate extending above the substrate, wherein the floating gate also extends above a portion of the vertical selection gate, over a non-zero overlap distance, the memory cell comprising a doped region implanted at the intersection of a vertical channel region extending opposite the selection gate and a horizontal channel region extending opposite the floating gate.

公开(公告)号：US10038372B2

公开(公告)日：2018-07-31

申请号：US15363631

申请日：2016-11-29

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Paola Cavaleri

IPC: H02M3/07

CPC classification number: H02M3/07 ,  G11C5/145 ,  G11C16/30

Abstract: A charge pump circuit can be controlled by a control signal that is generated from a first signal coming from and output signal of the charge pump circuit, from a reference signal, and from a clock signal. The generation of the control signal includes a comparison of the reference signal and of the first signal in tempo with a timing signal coming from the clock signal.

公开(公告)号：US10002906B2

公开(公告)日：2018-06-19

申请号：US15365143

申请日：2016-11-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier

IPC: G11C11/36 ,  H01L27/24 ,  H01L27/12 ,  H01L45/00

CPC classification number: H01L27/2409 ,  H01L27/1203 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/16

Abstract: The array of diodes comprises a matrix plane of diodes arranged according to columns in a first direction and according to rows in a second direction orthogonal to the first direction. The said diodes comprise a cathode region of a first type of conductivity and an anode region of a second type of conductivity, the said cathode and anode regions being superposed and disposed on an insulating layer situated on top of a semiconductor substrate.

公开(公告)号：US09941012B2

公开(公告)日：2018-04-10

申请号：US15453663

申请日：2017-03-08

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier

IPC: H01L29/66 ,  G11C16/26 ,  G11C7/18 ,  G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  G11C16/08 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/535 ,  H01L27/11556 ,  H01L29/423 ,  H01L27/02

CPC classification number: G11C16/26 ,  G11C7/18 ,  G11C16/0408 ,  G11C16/0433 ,  G11C16/08 ,  H01L21/76816 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/42324

Abstract: Non-volatile memory including rows and columns of memory cells, the columns of memory cells including pairs of twin memory cells including a common selection gate. According to the disclosure, two bitlines are provided per column of memory cells. The adjacent twin memory cells of the same column are not connected to the same bitline while the adjacent non-twin memory cells of the same column are connected to the same bitline.

公开(公告)号：US09875798B2

公开(公告)日：2018-01-23

申请号：US15140856

申请日：2016-04-28

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Gineuve Alieri

IPC: G11C14/00 ,  G11C16/16 ,  G11C29/00 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C14/0018 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C29/76 ,  G11C29/785 ,  G11C29/789 ,  G11C29/82 ,  G11C29/84 ,  G11C29/846

Abstract: A non-volatile memory is erasable by page and equipped with a row redundancy mechanism. In the case of the detection of a defective row of the memory plane, the storing of the address of the row in a non-volatile register is carried out and a redundant row having a new address is assigned. In the case of an attempt to write to the defective row, a write to the redundant row is carried out. When writing to the redundant row, the new content of the redundant row is loaded into a volatile memory and, following an operation for writing to any other row of the memory plane, a re-loading of the new content of the redundant row into the volatile memory.

公开(公告)号：US20180005684A1

公开(公告)日：2018-01-04

申请号：US15389751

申请日：2016-12-23

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Antonino Conte ,  Enrico Castaldo ,  Raul Andres Bianchi ,  Francesco La Rosa

IPC: G11C11/24

CPC classification number: G11C11/24 ,  G04F10/10

Abstract: A reading circuit for a charge-retention circuit stage is provided with a storage capacitor coupled between a first biasing terminal and a floating node, and a discharge element coupled between the floating node and a reference terminal. The reading circuit further has an operational amplifier having a first input terminal that is coupled to the floating node and receives a reading voltage, a second input terminal receives a reference voltage, and an output terminal on which it supplies an output voltage, the value of which is a function of the comparison between the reading voltage and the reference voltage and indicative of a residual charge in the storage capacitor. A shifting stage shifts the value of the reading voltage of the floating node, before the comparison is made between the reading voltage and the reference voltage for supplying the output voltage.

公开(公告)号：US20170352703A1

公开(公告)日：2017-12-07

申请号：US15365143

申请日：2016-11-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier

IPC: H01L27/24 ,  H01L27/12 ,  H01L45/00

CPC classification number: H01L27/2409 ,  H01L27/1203 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/16

Abstract: The array of diodes comprises a matrix plane of diodes arranged according to columns in a first direction and according to rows in a second direction orthogonal to the first direction. The said diodes comprise a cathode region of a first type of conductivity and an anode region of a second type of conductivity, the said cathode and anode regions being superposed and disposed on an insulating layer situated on top of a semiconductor substrate.

公开(公告)号：US09714976B2

公开(公告)日：2017-07-25

申请号：US14599116

申请日：2015-01-16

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa

IPC: G01R31/28 ,  G06F21/55 ,  G06F21/75 ,  G06F21/77 ,  G11C11/417 ,  G01R31/40 ,  G11C5/06 ,  G11C11/412

CPC classification number: G01R31/282 ,  G01R31/40 ,  G06F21/552 ,  G06F21/554 ,  G06F21/75 ,  G06F21/77 ,  G11C5/06 ,  G11C11/412 ,  G11C11/417

Abstract: A device for detecting a fault attack, including: a circuit for detecting an interruption of a power supply; a circuit for comparing the duration of the interruption with a first threshold; and a counter of the number of successive interruptions of the power supply having a duration which does not exceed the first threshold.