公开(公告)号：US11714760B2

公开(公告)日：2023-08-01

申请号：US16882264

申请日：2020-05-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen Bhoria ,  Timothy David Anderson ,  Pete Michael Hippleheuser

IPC: G06F12/0811 ,  G06F9/30 ,  G06F12/0888 ,  G06F12/0891 ,  G06F9/54 ,  G06F12/02 ,  G06F12/128 ,  G06F12/0817 ,  G06F12/0804 ,  G11C7/10 ,  G11C29/42 ,  G11C29/44 ,  G06F11/10 ,  G06F12/0855 ,  G06F12/12 ,  G06F12/0806 ,  G06F12/0815 ,  G06F12/0853 ,  G06F13/16 ,  G06F12/121 ,  G06F12/0884 ,  G06F12/0897 ,  G06F12/0895 ,  G06F12/0864 ,  G11C7/22 ,  G11C5/06 ,  G06F15/80 ,  G06F12/0802

CPC classification number: G06F12/0811 ,  G06F9/3001 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/546 ,  G06F11/1064 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0292 ,  G06F12/0802 ,  G06F12/082 ,  G06F12/0804 ,  G06F12/0806 ,  G06F12/0815 ,  G06F12/0853 ,  G06F12/0855 ,  G06F12/0864 ,  G06F12/0884 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/12 ,  G06F12/121 ,  G06F12/128 ,  G06F13/1605 ,  G06F13/1642 ,  G06F13/1673 ,  G06F13/1689 ,  G06F15/8069 ,  G11C5/066 ,  G11C7/10 ,  G11C7/106 ,  G11C7/1015 ,  G11C7/1075 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/222 ,  G11C29/42 ,  G11C29/44 ,  G06F2212/1016 ,  G06F2212/1021 ,  G06F2212/1024 ,  G06F2212/1041 ,  G06F2212/1044 ,  G06F2212/301 ,  G06F2212/454 ,  G06F2212/608 ,  G06F2212/6032 ,  G06F2212/62

Abstract: Methods, apparatus, systems and articles of manufacture to reduce bank pressure using aggressive write merging are disclosed. An example apparatus includes a first cache storage; a second cache storage; a store queue coupled to at least one of the first cache storage and the second cache storage and operable to: receive a first memory operation; process the first memory operation for storing the first set of data in at least one of the first cache storage and the second cache storage; receive a second memory operation; and prior to storing the first set of data in the at least one of the first cache storage and the second cache storage, merge the first memory operation and the second memory operation.

公开(公告)号：US11687457B2

公开(公告)日：2023-06-27

申请号：US17460439

申请日：2021-08-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok Chachad ,  David Matthew Thompson ,  Naveen Bhoria

IPC: G06F12/08 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/128 ,  G06F12/0817 ,  G06F12/084 ,  G06F9/30 ,  G06F11/30 ,  G06F12/0808 ,  G06F13/16 ,  G06F9/38 ,  G06F9/46 ,  G06F9/54 ,  G06F12/0895 ,  G06F12/0831

CPC classification number: G06F12/0811 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/3867 ,  G06F9/467 ,  G06F9/544 ,  G06F9/546 ,  G06F11/3037 ,  G06F12/084 ,  G06F12/0808 ,  G06F12/0815 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/0895 ,  G06F12/128 ,  G06F13/1668 ,  G06F2212/1021 ,  G06F2212/608

Abstract: A system includes a non-coherent component; a coherent, non-caching component; a coherent, caching component; and a level two (L2) cache subsystem coupled to the non-coherent component, the coherent, non-caching component, and the coherent, caching component. The L2 cache subsystem includes a L2 cache; a shadow level one (L1) main cache; a shadow L1 victim cache; and a L2 controller. The L2 controller is configured to receive and process a first transaction from the non-coherent component; receive and process a second transaction from the coherent, non-caching component; and receive and process a third transaction from the coherent, caching component.

公开(公告)号：US20220137970A1

公开(公告)日：2022-05-05

申请号：US17577482

申请日：2022-01-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen Bhoria ,  Dheera Balasubramanian Samudrala ,  Duc Bui ,  Rama Venkatasubramanian

IPC: G06F9/30 ,  G11C11/409 ,  G06F12/02 ,  G06F16/31 ,  G06F16/901 ,  G06F16/41 ,  G06F9/445 ,  G06F9/38

Abstract: A digital data processor includes an instruction memory storing instructions specifying a data processing operation and a data operand field, an instruction decoder coupled to the instruction memory for recalling instructions from the instruction memory and determining the operation and the data operand, and an operational unit coupled to a data register file and to an instruction decoder to perform a data processing operation upon an operand corresponding to an instruction decoded by the instruction decoder and storing results of the data processing operation. The operational unit is configured to perform a table write in response to a look up table initialization instruction by duplicating at least one data element from a source data register to create duplicated data elements, and writing the duplicated data elements to a specified location in a specified number of at least one table and a corresponding location in at least one other table.

公开(公告)号：US11144456B2

公开(公告)日：2021-10-12

申请号：US16882229

申请日：2020-05-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok Chachad ,  David Matthew Thompson ,  Naveen Bhoria ,  Peter Michael Hippleheuser

IPC: G06F12/0811 ,  G06F12/0815 ,  G06F12/128 ,  G06F12/0817 ,  G06F12/084 ,  G06F9/30 ,  G06F11/30 ,  G06F12/0808 ,  G06F13/16 ,  G06F9/38 ,  G06F9/46 ,  G06F9/54 ,  G06F12/0895

Abstract: An apparatus includes a CPU core and a L1 cache subsystem including a L1 main cache, a L1 victim cache, and a L1 controller. The apparatus includes a L2 cache subsystem including a L2 main cache, a shadow L1 main cache, a shadow L1 victim cache, and a L2 controller configured to receive a read request from the L1 controller as a single transaction. Read request includes a read address, a first indication of an address and a coherence state of a cache line A to be moved from the L1 main cache to the L1 victim cache to allocate space for data returned in response to the read request, and a second indication of an address and a coherence state of a cache line B to be removed from the L1 victim cache in response to the cache line A being moved to the L1 victim cache.

公开(公告)号：US10963255B2

公开(公告)日：2021-03-30

申请号：US16297824

申请日：2019-03-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen Bhoria ,  Kai Chirca ,  Timothy D. Anderson ,  Duc Bui ,  Abhijeet A. Chachad ,  Son Hung Tran

IPC: G06F9/34 ,  G06F11/00 ,  G06F12/0811 ,  G06F12/0875 ,  G06F9/30 ,  G06F9/38 ,  G06F12/0897 ,  G06F9/32 ,  G06F11/10 ,  G06F9/345

Abstract: Techniques related to executing a plurality of instructions by a processor comprising receiving a first instruction configured to cause the processor to output a first data value to a first address in a first data cache, outputting, by the processor, the first data value to a second address in a second data cache, receiving a second instruction configured to cause a streaming engine associated with the processor to prefetch data from the first data cache, determining that the first data value has not been outputted from the second data cache to the first data cache, stalling execution of the second instruction, receiving an indication, from the second data cache, that the first data value has been output from the second data cache to the first data cache, and resuming execution of the second instruction based on the received indication.

公开(公告)号：US20200371948A1

公开(公告)日：2020-11-26

申请号：US16882252

申请日：2020-05-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen Bhoria ,  Timothy David Anderson ,  Pete Michael Hippleheuser

IPC: G06F12/0888 ,  G06F12/0891 ,  G06F12/0895 ,  G06F9/54 ,  G06F9/30 ,  G11C7/10 ,  G11C7/22

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to forward and invalidate inflight data in a store queue. An example apparatus includes a cache storage, a cache controller coupled to the cache storage and operable to receive a first memory operation, determine that the first memory operation corresponds to a read miss in the cache storage, determine a victim address in the cache storage to evict in response to the read miss, issue a read-invalidate command that specifies the victim address, compare the victim address to a set of addresses associated with a set of memory operations being processed by the cache controller, and in response to the victim address matching a first address of the set of addresses corresponding to a second memory operation of the set of memory operations, provide data associated with the second memory operation.

公开(公告)号：US20200371927A1

公开(公告)日：2020-11-26

申请号：US16882380

申请日：2020-05-22

Applicant: Texas Instruments Incorporated

Inventor： Abhijeet Ashok Chachad ,  David Matthew Thompson ,  Naveen Bhoria

IPC: G06F12/0811 ,  G06F12/0817 ,  G06F12/1081 ,  G06F21/79 ,  G06F9/46

Abstract: In described examples, a coherent memory system includes a central processing unit (CPU) and first and second level caches. The CPU is arranged to execute program instructions to manipulate data in at least a first or second secure context. Each of the first and second caches stores a secure code for indicating the at least first or second secure contexts by which data for a respective cache line is received. The first and second level caches maintain coherency in response to comparing the secure codes of respective lines of cache and executing a cache coherency operation in response.

公开(公告)号：US10162641B2

公开(公告)日：2018-12-25

申请号：US15429205

申请日：2017-02-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy D. Anderson ,  Joseph Zbiciak ,  Duc Quang Bui ,  Abhijeet A. Chachad ,  Kai Chirca ,  Naveen Bhoria ,  Matthew D. Pierson ,  Daniel Wu ,  Ramakrishnan Venkatasubramanian

IPC: G06F9/312 ,  G06F12/12 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F11/00 ,  G06F9/32 ,  G06F12/0875 ,  G06F12/0897 ,  G06F11/10

Abstract: This invention addresses implements a range of interesting technologies into a single block. Each DSP CPU has a streaming engine. The streaming engines include: a SE to L2 interface that can request 512 bits/cycle from L2; a loose binding between SE and L2 interface, to allow a single stream to peak at 1024 bits/cycle; one-way coherence where the SE sees all earlier writes cached in system, but not writes that occur after stream opens; full protection against single-bit data errors within its internal storage via single-bit parity with semi-automatic restart on parity error.

公开(公告)号：US20180129608A9

公开(公告)日：2018-05-10

申请号：US14874842

申请日：2015-10-05

Applicant: Texas Instruments Incorporated

Inventor： Raguram Damodaran ,  Joseph Raymond Michael Zbiciak ,  Naveen Bhoria

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0888 ,  G06F12/0862 ,  G06F12/0897 ,  G06F12/12 ,  G06F12/121 ,  G06F2212/1021 ,  G06F2212/6022 ,  G06F2212/70

Abstract: The level one memory controller maintains a local copy of the cacheability bit of each memory attribute register. The level two memory controller is the initiator of all configuration read/write requests from the CPU. Whenever a configuration write is made to a memory attribute register, the level one memory controller updates its local copy of the memory attribute register.

公开(公告)号：US20170097894A1

公开(公告)日：2017-04-06

申请号：US14874842

申请日：2015-10-05

Applicant: Texas Instruments Incorporated

Inventor： Raguram Damodaran ,  Joseph Raymond Michael Zbiciak ,  Naveen Bhoria

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0888 ,  G06F12/0862 ,  G06F12/0897 ,  G06F12/12 ,  G06F12/121 ,  G06F2212/1021 ,  G06F2212/6022 ,  G06F2212/70

Abstract: The level one memory controller maintains a local copy of the cacheability bit of each memory attribute register. The level two memory controller is the initiator of all configuration read/write requests from the CPU. Whenever a configuration write is made to a memory attribute register, the level one memory controller updates its local copy of the memory attribute register.