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    Conductive metal oxide gate ferroelectric memory transistor
    102.
    发明授权
    Conductive metal oxide gate ferroelectric memory transistor 失效
    导电金属氧化物栅极铁电存储晶体管

    公开(公告)号：US07297602B2

    公开(公告)日：2007-11-20

    申请号：US10659547

    申请日：2003-09-09

    申请人： Sheng Teng Hsu ,  Tingkai Li

    发明人： Sheng Teng Hsu ,  Tingkai Li

    IPC分类号： H01L21/331 ,  H01L21/335

    CPC分类号： G11C11/22 ,  H01L21/28273 ,  H01L21/28291 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66825 ,  H01L29/6684 ,  H01L29/78391

    摘要： The present invention discloses a ferroelectric transistor having a conductive oxide in the place of the gate dielectric. The conductive oxide gate ferroelectric transistor can have a three-layer metal/ferroelectric/metal or a two-layer metal/ferroelectric on top of the conductive oxide gate. By replacing the gate dielectric with a conductive oxide, the bottom gate of the ferroelectric layer is conductive through the conductive oxide to the silicon substrate, thus minimizing the floating gate effect. The memory retention degradation related to the leakage current associated with the charges trapped within the floating gate is eliminated. The fabrication of the ferroelectric transistor by a gate etching process or a replacement gate process is also disclosed.

    摘要翻译： 本发明公开了一种具有导电氧化物代替栅电介质的铁电晶体管。 导电氧化物栅极铁电晶体管可以在导电氧化物栅极的顶部上具有三层金属/铁电/金属或两层金属/铁电体。 通过用导电氧化物代替栅极电介质，铁电层的底栅通过导电氧化物导电到硅衬底，从而最小化浮栅效应。 消除了与在浮动栅极内捕获的电荷相关的泄漏电流相关的存储器保持性降低。 还公开了通过栅极蚀刻工艺或替代栅极工艺制造铁电晶体管。

    Triple-junction filterless CMOS imager cell
    103.
    发明申请
    Triple-junction filterless CMOS imager cell 失效
    三联无滤膜CMOS成像单元

    公开(公告)号：US20070218580A1

    公开(公告)日：2007-09-20

    申请号：US11580407

    申请日：2006-10-13

    申请人： Sheng Teng Hsu ,  Jong-Jan Lee

    发明人： Sheng Teng Hsu ,  Jong-Jan Lee

    IPC分类号： H01L21/00

    CPC分类号： H01L27/14603 ,  H01L27/14632 ,  H01L27/14645 ,  H01L27/14647 ,  H01L27/14683 ,  H01L27/14689

    摘要： A triple-junction complimentary metal-oxide-semiconductor (CMOS) filterless color imager cell is provided. The imager cell is made from a bulk silicon (Si) substrate. A photodiode set including a first, second, and third photodiode are formed as a triple-junction structure in the Si substrate. A transistor set is connected to the photodiode set, and detects an independent output signal for each photodiode. Typically, the transistor set is formed in the top surface of the substrate. For example, the Si substrate may be a p-doped Si substrate, and the photodiode triple-junction structure includes the first photodiode forming a pn junction from an n+-doped region at the Si substrate top surface, to an underlying p-doped region. The second photodiode forms a pn junction from the p-doped region to an underlying n-well, and the third photodiode forms a pn junction from the n-well to the underlying p-doped Si substrate.

    摘要翻译： 提供三结互补金属氧化物半导体（CMOS）无滤色器彩色成像器单元。 成像器单元由体硅（Si）衬底制成。 在Si衬底中形成包括第一，第二和第三光电二极管的光电二极管组作为三结结构。 晶体管组连接到光电二极管组，并检测每个光电二极管的独立输出信号。 通常，晶体管组形成在衬底的顶表面中。 例如，Si衬底可以是p掺杂的Si衬底，并且光电二极管三结结构包括第一光电二极管，其形成从Si衬底顶表面处的n +掺杂区域到下一个p掺杂区域的pn结 。 第二光电二极管形成从p掺杂区域到下面的n阱的pn结，并且第三光电二极管形成从n阱到下面的p掺杂Si衬底的pn结。

    Ultrathin SOI transistor and method of making the same
    105.
    发明授权
    Ultrathin SOI transistor and method of making the same 失效
    超薄SOI晶体管及其制作方法

    公开(公告)号：US07247530B2

    公开(公告)日：2007-07-24

    申请号：US11050495

    申请日：2005-02-01

    申请人： Sheng Teng Hsu ,  Jong-Jan Lee

    发明人： Sheng Teng Hsu ,  Jong-Jan Lee

    IPC分类号： H01L21/338

    CPC分类号： H01L29/66772 ,  Y10S438/926

    摘要： A method of fabricating an ultrathin SOI memory transistor includes preparing a substrate, including forming an ultrathin SOI layer of the substrate; adjusting the threshold voltage of the SOI layer; depositing a layer of silicon oxide on the SOI layer; patterning and etching the silicon oxide layer to form a sacrificial oxide gate in a gate region; depositing a layer of silicon nitride and forming the silicon nitride into a silicon nitride sidewall for the sacrificial oxide gate; depositing and smoothing a layer of amorphous silicon; selectively etching the sacrificial gate oxide; growing a layer of oxide in the gate region; depositing and smoothing a second layer of amorphous silicon; patterning and etching the second layer of amorphous silicon; implanting ion to form a source region and a drain region; annealing the structure; and depositing a layer of passivation oxide.

    摘要翻译： 制造超薄SOI存储晶体管的方法包括：制备衬底，包括形成衬底的超薄SOI层; 调整SOI层的阈值电压; 在SOI层上沉积一层氧化硅; 图案化和蚀刻氧化硅层以在栅极区域中形成牺牲氧化物栅极; 沉积氮化硅层并将氮化硅形成用于牺牲氧化物栅极的氮化硅侧壁; 沉积和平滑一层非晶硅; 选择性地蚀刻牺牲栅极氧化物; 在栅极区生长一层氧化物; 沉积和平滑第二层非晶硅; 图案化和蚀刻第二层非晶硅; 注入离子以形成源区和漏区; 退火结构; 并沉积一层钝化氧化物。

    Method to form thick relaxed SiGe layer with trench structure
    106.
    发明授权
    Method to form thick relaxed SiGe layer with trench structure 失效
    形成具有沟槽结构的厚松弛SiGe层的方法

    公开(公告)号：US07226504B2

    公开(公告)日：2007-06-05

    申请号：US10062336

    申请日：2002-01-31

    申请人： Jer-Shen Maa ,  Douglas James Tweet ,  Tingkai Li ,  Jong-Jan Lee ,  Sheng Teng Hsu

    发明人： Jer-Shen Maa ,  Douglas James Tweet ,  Tingkai Li ,  Jong-Jan Lee ,  Sheng Teng Hsu

    IPC分类号： C30B33/02

    CPC分类号： H01L21/3247 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02694 ,  H01L21/324

    摘要： A method of forming a SiGe layer having a relatively high germanium content and a relatively low threading dislocation density includes preparing a silicon substrate; depositing a layer of SiGe to a thickness of between about 100 nm to 500 nm, wherein the germanium content of the SiGe layer is greater than 20%, by atomic ratio; implanting H+ ions into the SiGe layer at a dose of between about 1·1016 cm−2 to 5·1016 cm−2, at an energy of between about 20 keV to 45 keV; patterning the SiGe layer with photoresist; plasma etching the structure to form trenches about regions; removing the photoresist; and thermal annealing the substrate and SiGe layer, to relax the SiGe layer, in an inert atmosphere at a temperature of between about 650° C. to 950° C. for between about 30 seconds and 30 minutes.

    摘要翻译： 形成具有较高锗含量和较低穿透位错密度的SiGe层的方法包括制备硅衬底; 将SiGe层沉积至约100nm至500nm的厚度，其中SiGe层的锗含量按原子比大于20％; 将H +离子以约1.10×16cm -2至0.0010±0.2cm的剂量注入SiGe层中， SUP>，在约20keV至45keV之间的能量; 用光致抗蚀剂图案化SiGe层; 等离子体蚀刻结构以形成关于区域的沟槽; 去除光致抗蚀剂; 以及对基板和SiGe层进行热退火，以在惰性气氛中在约650℃至950℃的温度下放置SiGe层约30秒至30分钟。

    Strained silicon devices transfer to glass for display applications
    107.
    发明授权
    Strained silicon devices transfer to glass for display applications 失效
    应变硅器件转移到玻璃上进行显示应用

    公开(公告)号：US07176072B2

    公开(公告)日：2007-02-13

    申请号：US11046411

    申请日：2005-01-28

    申请人： Jong-Jan Lee ,  Jer-Shen Maa ,  Sheng Teng Hsu

    发明人： Jong-Jan Lee ,  Jer-Shen Maa ,  Sheng Teng Hsu

    IPC分类号： H01L21/84 ,  H01L21/00 ,  H01L21/658

    CPC分类号： H01L27/1266 ,  H01L27/1203 ,  H01L27/1214 ,  H01L29/78687

    摘要： A method of fabricating strained silicon devices for transfer to glass for display applications includes preparing a wafer having a silicon substrate thereon; forming a relaxed SiGe layer on the silicon substrate; forming a strained silicon layer on the relaxed SiGe layer; fabricating an IC device on the strained silicon layer; depositing a dielectric layer on the wafer to cover a gate module of the IC device; smoothing the dielectric; implanting ions to form a defect layer; cutting the wafer into individual silicon dies; preparing a glass panel and the silicon dies for bonding; bonding the silicon dies onto the glass panel to form a bonded structure; annealing the bonded structure; splitting the bonded structure along the defect layer; removing the remaining silicon layer from the silicon substrate and relaxed SiGe layer on the silicon die on the glass panel; and completing the glass panel circuitry.

    摘要翻译： 制造用于转移到用于显示器应用的玻璃的应变硅器件的方法包括制备其上具有硅衬底的晶片; 在硅衬底上形成松弛的SiGe层; 在松弛的SiGe层上形成应变硅层; 在应变硅层上制造IC器件; 在所述晶片上沉积介电层以覆盖所述IC器件的栅极模块; 平滑电介质; 注入离子以形成缺陷层; 将晶片切割成单独的硅模具; 制备玻璃面板和用于接合的硅模具; 将硅模具接合到玻璃面板上以形成接合结构; 退火键合结构; 沿着缺陷层分离粘结结构; 从硅衬底去除剩余的硅层并在玻璃面板上的硅晶片上松弛SiGe层; 并完成玻璃面板电路。

    One mask Pt/PCMO/Pt stack etching process for RRAM applications
    108.
    发明授权
    One mask Pt/PCMO/Pt stack etching process for RRAM applications 有权
    用于RRAM应用的一个掩模Pt / PCMO / Pt堆叠蚀刻工艺

    公开(公告)号：US07169637B2

    公开(公告)日：2007-01-30

    申请号：US10883228

    申请日：2004-07-01

    申请人： Fengyan Zhang ,  Lisa H. Stecker ,  Bruce D. Ulrich ,  Sheng Teng Hsu

    发明人： Fengyan Zhang ,  Lisa H. Stecker ,  Bruce D. Ulrich ,  Sheng Teng Hsu

    IPC分类号： H01L21/06 ,  H01L21/461

    CPC分类号： H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1675

    摘要： A one-mask etching method for use with a PCMO-containing RRAM to reduce stack side-wall residuals, includes preparing a substrate, taken from the group of substrates consisting of silicon, silicon dioxide and polysilicon; depositing a bottom electrode on the substrate; depositing a PCMO layer on the bottom electrode; depositing a top electrode on the PCMO layer; depositing a hard mask on the top electrode; depositing and patterning a photoresist layer on the hard mask; etching the hard mask; etching the top electrode using a first etching process having an etching atmosphere consisting of Ar, O2, and Cl2; etching the PCMO layer using an etching process taken from the group of etching processes consisting of the first etching process and a second etching process having an etching atmosphere consisting of Ar and O2. etching the bottom electrode using the first etching process; and completing the RRAM device.

    摘要翻译： 包含含PCMO的RRAM以减少堆叠侧壁残留物的单掩模蚀刻方法包括制备从由硅，二氧化硅和多晶硅组成的一组衬底取得的衬底; 在底物上沉积底部电极; 在底部电极上沉​​积PCMO层; 在PCMO层上沉积顶部电极; 在顶部电极上沉​​积硬掩模; 在硬掩模上沉积和图案化光致抗蚀剂层; 蚀刻硬掩模; 使用具有由Ar，O 2和Cl 2组成的蚀刻气氛的第一蚀刻工艺蚀刻顶部电极; 使用从由第一蚀刻工艺和由Ar和O 2组成的蚀刻气氛的第二蚀刻工艺组成的蚀刻工艺组中的蚀刻工艺来蚀刻PCMO层。 使用第一蚀刻工艺蚀刻底部电极; 并完成RRAM设备。

    Surface-normal optical path structure for infrared photodetection
    110.
    发明授权
    Surface-normal optical path structure for infrared photodetection 有权
    用于红外光电检测的表面法线光路结构

    公开(公告)号：US07129488B2

    公开(公告)日：2006-10-31

    申请号：US10746952

    申请日：2003-12-23

    申请人： Jong Jan Lee ,  Jer-Shen Maa ,  Douglas J. Tweet ,  Sheng Teng Hsu

    发明人： Jong Jan Lee ,  Jer-Shen Maa ,  Douglas J. Tweet ,  Sheng Teng Hsu

    IPC分类号： G01J5/20 ,  G01J5/08

    CPC分类号： H01L31/105 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02639 ,  H01L27/14627 ,  H01L27/14643 ,  H01L31/02327 ,  H01L31/028 ,  H01L31/035281 ,  H01L31/108 ,  H01L31/109 ,  H01L31/1812 ,  Y02E10/547

    摘要： A SiGe surface-normal optical path photodetector structure and a method for forming the SiGe optical path normal structure are provided. The method comprises: forming a Si substrate with a surface; forming a Si feature, normal with respect to the Si substrate surface, such as a via, trench, or pillar; depositing SiGe overlying the Si normal feature to a thickness in the range of 5 to 1000 nanometers (nm); and, forming a SiGe optical path normal structure having an optical path length in the range of 0.1 to 10 microns. Typically, the SiGe has a Ge concentration in the range from 5 to 100%. The Ge concentration may be graded to increase with respect to the deposition thickness. For example, the SiGe may have a 20% concentration of Ge at the Si substrate interface, a 30% concentration of Ge at a SiGe film top surface, and a thickness of 400 nm.

    摘要翻译： 提供SiGe表面法线光路检测器结构和形成SiGe光路法线结构的方法。 该方法包括：用表面形成Si衬底; 形成Si特征，相对于诸如通孔，沟槽或柱的Si衬底表面是正常的; 将Si覆盖Si正常特征的SiGe沉积到5至1000纳米（nm）范围内的厚度; 并且形成光程长度为0.1〜10微米的SiGe光路法线结构。 通常，SiGe的Ge浓度为5〜100％。 Ge浓度可以相对于沉积厚度而分级增加。 例如，SiGe可以在Si衬底界面处具有20％的Ge浓度，在SiGe膜顶表面上可以具有30％的Ge浓度，并且厚度为400nm。