Analogue-to-digital converter
    101.
    发明授权

    公开(公告)号:US09923574B2

    公开(公告)日:2018-03-20

    申请号:US15663411

    申请日:2017-07-28

    Abstract: This application relates to analog-to-digital converters (ADCs). An ADC 200 has a first converter (201) for receiving an analog input signal (AIN) and outputting a time encode signal (DT), such as a pulse-width-modulated (PWM) signal, based on input signal and a first conversion gain setting (GIN). In some embodiments the first converter has a PWM modulator (401) for generating a PWM signal such that the input signal is encoded by pulse widths that can vary continuously in time. A second converter (202) receives the time encoded signal and outputs a digital output signal (DOUT) based on the time encoded signal (DT) and a second conversion gain setting (GO). The second converter may have a first PWM-to-digital modulator (403). A gain allocation block (204) generates the first and second conversion gain settings based on the time encoded signal (DT). The gain allocation block (204) may have a second PWM-to-digital modulator (203) which may be of lower latency and/or lower resolution that the first PWM-to-digital modulator (403).

    Minimizing startup transients in an audio playback path

    公开(公告)号:US09854357B1

    公开(公告)日:2017-12-26

    申请号:US15195626

    申请日:2016-06-28

    Abstract: A method may be provided for powering up or down a playback path comprising a digital-to-analog converter (DAC) for generating a non-ground-centered analog intermediate voltage centered at a common-mode voltage and coupled to a driver for generating a ground-centered playback path output voltage at an output of the driver wherein the output of the driver is clamped via a finite impedance to a ground voltage. The method may include transitioning continuously or in a plurality of discrete steps the analog intermediate voltage from an initial voltage to the common-mode voltage such that the transitioning is substantially inaudible at the output of the driver. A method for operating an output clamp of an output driver stage of a playback path may include transitioning continuously or in a plurality of discrete steps an impedance of the output clamp in order to match an output offset of the output driver stage in order to minimize audio artifacts appearing at an output of the output driver stage.

    Charge pump circuit
    108.
    发明授权

    公开(公告)号:US09685856B2

    公开(公告)日:2017-06-20

    申请号:US15205439

    申请日:2016-07-08

    Abstract: A bipolar output charge pump circuit having a network of switching paths for selectively connecting an input node and a reference node for connection to an input voltage, a first pair of output nodes and a second pair of output nodes, and two pairs of flying capacitor nodes, and a controller for controlling the switching of the network of switching paths. The controller is operable to control the network of switching paths when in use with two flying capacitors connected to the two pairs of flying capacitor nodes, to provide a first bipolar output voltage at the first pair of output nodes and a second bipolar output voltage at the second pair of bipolar output nodes.

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