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公开(公告)号：US09923574B2
公开(公告)日：2018-03-20
申请号：US15663411
申请日：2017-07-28
Inventor： John Paul Lesso , Emmanuel Philippe Christian Hardy
CPC classification number: H03M7/30 , H03K7/08 , H03K9/08 , H03M1/18 , H03M1/181 , H03M1/50 , H03M1/504 , H03M3/484 , H03M2201/00
Abstract: This application relates to analog-to-digital converters (ADCs). An ADC 200 has a first converter (201) for receiving an analog input signal (AIN) and outputting a time encode signal (DT), such as a pulse-width-modulated (PWM) signal, based on input signal and a first conversion gain setting (GIN). In some embodiments the first converter has a PWM modulator (401) for generating a PWM signal such that the input signal is encoded by pulse widths that can vary continuously in time. A second converter (202) receives the time encoded signal and outputs a digital output signal (DOUT) based on the time encoded signal (DT) and a second conversion gain setting (GO). The second converter may have a first PWM-to-digital modulator (403). A gain allocation block (204) generates the first and second conversion gain settings based on the time encoded signal (DT). The gain allocation block (204) may have a second PWM-to-digital modulator (203) which may be of lower latency and/or lower resolution that the first PWM-to-digital modulator (403).
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公开(公告)号：US09912312B2
公开(公告)日：2018-03-06
申请号：US14182850
申请日：2014-02-18
Applicant: Cirrus Logic, Inc.
Inventor： Ullas Pazhayaveetil , Jeffrey May , Gautham Kamath , John Christopher Tucker , Christian Larsen
CPC classification number: H02M3/158 , G01R21/06 , G01R27/2611 , G06F1/3203 , H02M3/156 , H03F3/187 , H03F3/2175 , H03G3/004
Abstract: A controller of a boost converter may be configured to dynamically adjust conditions within the boost converter by monitoring conditions in the boost converter. For example, the controller may determine an current inductance value for an inductor of the boost converter by monitoring a current through the inductor. When the inductance value of the inductor is known, a slope compensation value may be used in determining a transition time between charging the inductor of the boost converter and discharging the inductor.
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公开(公告)号：US09912232B2
公开(公告)日：2018-03-06
申请号：US15144725
申请日：2016-05-02
Inventor： Umar J. Lyles , Ullas Pazhayaveetil , Jeffrey May
Abstract: A combination of inductor current thresholds and circuitry for controlling the inductor based on the thresholds may be implemented in a power converter. One or more of the inductor current thresholds may be variable. An inductor current threshold may be varied as part of a search algorithm for identifying a value resulting in full scale operation of the inductor without exceeding a safe limit. After each cycle of the power converter, circuitry may determine which current thresholds have been exceeded and which have not been exceeded and then generate indication signals for each of the thresholds. Control logic may receive the indication signals and adjust one of the inductor current thresholds used to determine timing for disconnecting and reconnecting current through the inductor of the power converter.
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公开(公告)号：US09906196B2
公开(公告)日：2018-02-27
申请号：US15270631
申请日：2016-09-20
Inventor： Zhaohui He , Eric J. King , Siddharth Maru , John L. Melanson
CPC classification number: H03F3/217 , H03F1/04 , H03F1/34 , H03F3/185 , H03F3/2171 , H03F3/2173 , H03F3/45475 , H03F2200/351 , H03F2200/432 , H03F2203/45034 , H04R3/12 , H04R2420/03
Abstract: A switching power stage for producing a load voltage may include a first processing path having a first output, a second processing path having a second output, a first plurality of switches comprising at least a first switch coupled between the first output and a first load terminal and a second switch coupled between the first output and the second load terminal, a second plurality of switches comprising at least a third switch coupled between the second output and the first load terminal and a fourth switch coupled between the second output and the second load terminal, and a controller configured to control switches in order to generate the load voltage as a function of an input signal such that one of the first switch and the second switch operates in a linear region of operation and one of the third switch and the fourth switch operates in a saturated region of operation for a predominance of a dynamic rage of the load voltage.
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公开(公告)号：US09854357B1
公开(公告)日：2017-12-26
申请号：US15195626
申请日：2016-06-28
Inventor： Tejasvi Das , Anand Ilango
CPC classification number: H04R3/007 , H03F1/305 , H03F1/34 , H03F3/181 , H03F3/187 , H03F3/20 , H03F3/72 , H03F2200/03 , H03F2200/129 , H03F2200/381 , H03F2200/408 , H03G3/348 , H03M1/66
Abstract: A method may be provided for powering up or down a playback path comprising a digital-to-analog converter (DAC) for generating a non-ground-centered analog intermediate voltage centered at a common-mode voltage and coupled to a driver for generating a ground-centered playback path output voltage at an output of the driver wherein the output of the driver is clamped via a finite impedance to a ground voltage. The method may include transitioning continuously or in a plurality of discrete steps the analog intermediate voltage from an initial voltage to the common-mode voltage such that the transitioning is substantially inaudible at the output of the driver. A method for operating an output clamp of an output driver stage of a playback path may include transitioning continuously or in a plurality of discrete steps an impedance of the output clamp in order to match an output offset of the output driver stage in order to minimize audio artifacts appearing at an output of the output driver stage.
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Patent Agency Ranking
公开(公告)号：US09812114B2
公开(公告)日：2017-11-07
申请号：US15058866
申请日：2016-03-02
Inventor： Jeffrey D. Alderson , Jon D. Hendrix , Sang-Ik Terry Cho , Chin Huang Yong , John L. Melanson
IPC: A61F11/06 , G10K11/16 , G10K11/178
CPC classification number: G10K11/178 , G10K11/17885 , G10K2210/108 , G10K2210/1081 , G10K2210/3014 , G10K2210/3016 , G10K2210/3028 , G10K2210/3056
Abstract: A method may include adaptively generating an anti-noise signal for countering the effects of ambient audio sounds at an acoustic output of the transducer by adapting a response of an adaptive filter that filters a reference microphone signal in conformity with an error microphone signal and the reference microphone signal to minimize the ambient audio sounds in the error microphone, generating a scaled anti-noise signal by applying a scaling factor to the anti-noise signal, further adjusting the response of the adaptive filter independent of a source audio signal by altering an input to the coefficient control block of the adaptive filter to compensate for the scaling factor, and combining the scaled anti-noise signal with the source audio signal to generate an audio signal provided to the transducer.
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公开(公告)号：US09729164B2
公开(公告)日：2017-08-08
申请号：US14826996
申请日：2015-08-14
Inventor： Ramin Zanbaghi , Yousof Mortazavi , Aaron Brennan , John L. Melanson
CPC classification number: H03M1/14 , G06F3/16 , G11C27/024 , H03F3/005 , H03F3/45475 , H03F3/45959 , H03F2203/45421 , H03F2203/45512 , H03F2203/45544 , H03F2203/45551 , H03M1/124 , H03M1/1295 , H03M3/458 , H03M3/494 , H03M3/496 , H04R3/00 , H04R19/04 , H04R29/004 , H04R2499/11
Abstract: One method of processing microphone input in an ADC to determine microphone configuration is to process the microphone input signals in two processing paths, in which one processing path processes a difference between differential input signals and another processing path processes an average value of the differential input signals. The outputs of these processing paths may be combined to generate a digital signal representative of the analog signal from the microphone. The digital signal contains a digital version of the audio in the environment around the microphone, but may also be used to detect microphone topology and configure aspects of the processing paths to match the detected microphone topology. An apparatus for an ADC may implement the two processing paths as two delta-sigma modulator loops.
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公开(公告)号：US09685856B2
公开(公告)日：2017-06-20
申请号：US15205439
申请日：2016-07-08
Inventor： John P. Lesso , Peter J. Frith , John L. Pennock
CPC classification number: H02M3/07 , H02M1/00 , H02M2001/0083 , H02M2001/009 , H03F3/181
Abstract: A bipolar output charge pump circuit having a network of switching paths for selectively connecting an input node and a reference node for connection to an input voltage, a first pair of output nodes and a second pair of output nodes, and two pairs of flying capacitor nodes, and a controller for controlling the switching of the network of switching paths. The controller is operable to control the network of switching paths when in use with two flying capacitors connected to the two pairs of flying capacitor nodes, to provide a first bipolar output voltage at the first pair of output nodes and a second bipolar output voltage at the second pair of bipolar output nodes.
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公开(公告)号：US09673762B2
公开(公告)日：2017-06-06
申请号：US14920698
申请日：2015-10-22
Applicant: Cirrus Logic, Inc.
Inventor： Lingli Zhang , Huan Wang , Yongjie Cheng , Christian Larsen
CPC classification number: H03F3/185 , H03F1/0205 , H03F1/305 , H03F3/2171 , H03F2200/03 , H03F2200/351 , H03F2200/375
Abstract: A variable ramp up/down gain in a pre-power stage block of an audio amplifier may be used to reduce audible pops and clicks output by the audio amplifier. A controller may adjust the variable ramp up/down gain during operation of the audio amplifier. The variable ramp up/down gain may be implemented as a pulse width modulation (PWM) modulator/generator with a ramp-up and ramp-down gain under control of the controller. The variable ramp up/down gain smooths transitions of the offset between a pre-power stage block and a feedback loop and thus can reduce audible pops and clicks by reducing the offset that is amplified in the power stage block of the audio amplifier.
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公开(公告)号：US09666176B2
公开(公告)日：2017-05-30
申请号：US14026021
申请日：2013-09-13
Applicant: Cirrus Logic, Inc.
Inventor： Ali Abdollahzadeh Milani , Yang Lu , Dayong Zhou , Ning Li
IPC: G10K11/178 , H03F1/02 , H03F3/181 , H03F3/52
CPC classification number: G10K11/1788 , G10K11/17854 , G10K11/17881 , G10K11/17885 , G10K2210/1081 , G10K2210/30232 , G10K2210/3045 , G10K2210/3049 , H03F1/0211 , H03F3/181 , H03F3/52
Abstract: A processing circuit may include: (i) an adaptive filter having a response that generates an anti-noise signal from a reference microphone signal, wherein the response is shaped in conformity with the reference microphone signal and a playback corrected error, and wherein the playback corrected error is based on a difference between an error microphone signal and a secondary path estimate; (ii) a secondary path estimate filter configured to model an electro-acoustic path of a source audio signal and having a response that generates a secondary path estimate from the source audio signal; (iii) a secondary coefficient control block that shapes the response of the secondary path estimate filter in conformity with the source audio signal and the playback corrected error by adapting the response of the secondary path estimate filter to minimize the playback corrected error; and (iv) a noise injection portion for injecting a noise signal into the source audio signal, wherein the noise signal is shaped based on the playback corrected error.
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