公开(公告)号：US11810775B2

公开(公告)日：2023-11-07

申请号：US17443307

申请日：2021-07-23

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Yusheng Lin ,  Jerome Teysseyre

IPC分类号： H01L23/373 ,  H01L21/52 ,  H01L23/31 ,  H01L23/433 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/07 ,  H01L25/00 ,  H01L29/739 ,  H01L29/861 ,  H01L23/051 ,  H01L25/18 ,  H01L23/538 ,  H01L21/48 ,  H01L23/495

CPC分类号： H01L23/3735 ,  H01L21/52 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/4334 ,  H01L23/49822 ,  H01L24/20 ,  H01L25/0657 ,  H01L25/072 ,  H01L25/50 ,  H01L29/7393 ,  H01L29/861 ,  H01L2225/06589

摘要： A method includes disposing a semiconductor die between a first high voltage isolation carrier and a second high voltage isolation carrier, disposing a first molding material in a space between the semiconductor die and the first high voltage isolation carrier, and disposing a conductive spacer between the semiconductor die and the second high voltage isolation carrier. The method further includes encapsulating the first molding material and the conductive spacer with a second molding material.

公开(公告)号：US20230352433A1

公开(公告)日：2023-11-02

申请号：US17730342

申请日：2022-04-27

申请人： NANYA TECHNOLOGY CORPORATION

发明人： SHENG-HUI YANG

IPC分类号： H01L23/00

CPC分类号： H01L24/24 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/24011 ,  H01L2224/2405 ,  H01L2224/24146 ,  H01L2224/215

摘要： A semiconductor device structure includes a silicon layer disposed over a first semiconductor die, and a first mask layer disposed over the silicon layer. The semiconductor device structure also includes a second semiconductor die disposed over the first mask layer, and a through silicon via penetrating through the silicon layer and the first mask layer. A bottom surface of the through silicon via is greater than a top surface of the through silicon via, and the top surface of the through silicon via is greater than a cross-section of the through silicon via between and parallel to the top surface and the bottom surface of the through silicon via.

公开(公告)号：US11803682B2

公开(公告)日：2023-10-31

申请号：US17072792

申请日：2020-10-16

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Ta-Pen Guo ,  Chien-Ying Chen

IPC分类号： G06F30/30 ,  G06F30/392 ,  G03F1/70 ,  H01L23/50 ,  G06F30/398 ,  H01L23/00

CPC分类号： G06F30/392 ,  G03F1/70 ,  G06F30/398 ,  H01L23/50 ,  H01L24/20

摘要： A semiconductor device includes a first power rail, a second power rail, and a first cell. The first cell has a first first-type active region and a first second-type active region, and a first cell height of the first cell is defined as a pitch between the first power rail and the second power rail. The semiconductor device further includes a second cell having a second first-type active region and a second second-type active region, wherein the second first-type active region extends in a second row and a third row on a first side of the first row and has a first width in the column direction greater than a second width of the first first-type active region in the column direction. The semiconductor device also includes a third cell having a first portion and a second portion arranged in the second row and a fourth row, respectively.

公开(公告)号：US20230343689A1

公开(公告)日：2023-10-26

申请号：US18129840

申请日：2023-04-01

申请人： iCometrue Company Ltd.

发明人： Mou-Shiung Lin ,  Jin-Yuan Lee

IPC分类号： H01L23/498 ,  H01L23/00

CPC分类号： H01L23/49833 ,  H01L23/49816 ,  H01L23/49866 ,  H01L24/19 ,  H01L24/20

摘要： A chip package includes a first interconnection scheme; a plurality of first metal contacts under and on the first interconnection scheme and at a bottom surface of the chip package; a first semiconductor IC chip over the first interconnection scheme; a first connector over the first interconnection scheme and at a same horizontal level as the first semiconductor IC chip, wherein the first connector comprises a first substrate and a plurality of first through vias vertically extending through the first substrate of the first connector; a first polymer layer over the first interconnection scheme, wherein the first polymer layer has a top surface coplanar with a top surface of the first semiconductor IC chip, a top surface of the first substrate of the first connector and a top surface of each of the plurality of first through vias; and a second interconnection scheme on the top surface of the first polymer layer, the top surface of the first semiconductor IC chip, the top surface of the first connector and the top surface of each of the plurality of first through vias, wherein the second interconnection scheme comprises a plurality of second metal contacts at a top surface of the chip package.

公开(公告)号：US20230335539A1

公开(公告)日：2023-10-19

申请号：US18336435

申请日：2023-06-16

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Hsien-Wei CHEN ,  Li-Hsien HUANG

IPC分类号： H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H01L25/10 ,  H01L25/065

CPC分类号： H01L25/105 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/09 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0652 ,  H01L25/50 ,  H01L23/49816 ,  H01L23/49827 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/37001

摘要： A package structure and method for forming the same are provided. The package structure includes a package component, and a dummy die disposed over the package component. The package structure includes a device die adjacent to the dummy die, and a buffer layer formed below the dummy die. The buffer layer has a first surface and an opposite second surface, the first surface is in direct contact with a bottom surface of the dummy die and the second surface is separated from the package component. The package structure includes a package layer surrounding the device die, the dummy die and the buffer layer.

公开(公告)号：US20230335526A1

公开(公告)日：2023-10-19

申请号：US18132602

申请日：2023-04-10

申请人： SJ Semiconductor(Jiangyin) Corporation

发明人： Chengchung Lin ,  Jin Yang

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L21/56

CPC分类号： H01L24/20 ,  H01L24/19 ,  H01L23/3157 ,  H01L25/0655 ,  H01L21/56 ,  H01L2224/2101 ,  H01L2224/19

摘要： A high-density-interconnection (HDI) packaging structure and a method for preparing the same are provided. The method comprises: disposing a first metal array with a first pitch and a second metal array with a second pitch on chips; disposing a third metal array on a silicon connector, and bonding the silicon connector to cross the chips; forming a molding layer to cover the chips and the silicon connector; grinding the molding layer and the silicon connector to form ultra-thin silicon; forming vias in the molding layer, with the vias aligned to the second metal array; filling the vias with metal materials, wherein the metal materials are connected to the second metal array; forming metal pillars and connecting the metal pillars to an organic substrate. The present disclosure uses ultra-thin silicon as an intermediate connector to achieve fine interconnection between HDI chips at a pitch of 10 um or less.

公开(公告)号：US20230335453A1

公开(公告)日：2023-10-19

申请号：US18132295

申请日：2023-04-07

申请人： SJ Semiconductor(Jiangyin) Corporation

发明人： Yenheng Chen ,  Chengchung Lin

IPC分类号： H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01Q1/40 ,  H01Q1/38

CPC分类号： H01L23/3128 ,  H01L24/20 ,  H01L21/568 ,  H01L24/19 ,  H01Q1/40 ,  H01Q1/38 ,  H01L2224/21 ,  H01L2224/19

摘要： A packaging structure comprising a first antenna layer on a protective layer, a dielectric layer, a first plastic packaging layer over the first antenna layer, a second conductive pillar, a chip, a redistribution layer, and a second plastic packaging layer, the first conductive pillar is electrically connected to the first antenna layer, the dielectric layer is formed over the first conductive pillar, the second antenna layer is electrically connected to the first conductive pillar, the second conductive pillar is formed over the dielectric layer and electrically connected to the second antenna layer, the chip layer is formed over the dielectric layer, the redistribution layer is provided with conductive bumps and electrically connected to the chip and the second antenna layer, and the second plastic packaging layer encapsulates the second antenna layer and the chip. Chip and multiple antennas are packaged with one carrier substrate, reducing size.

公开(公告)号：US11791534B2

公开(公告)日：2023-10-17

申请号：US17392680

申请日：2021-08-03

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Feng-Wei Kuo ,  Wen-Shiang Liao

IPC分类号： H01Q1/22 ,  H01L21/56 ,  H01L21/48 ,  H01L21/683 ,  H01L21/027 ,  H01L23/498 ,  H01L23/66 ,  H01L23/31 ,  H01L23/29 ,  H01L23/00 ,  H01L23/538

CPC分类号： H01Q1/2283 ,  H01L21/0273 ,  H01L21/486 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/293 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/66 ,  H01L24/19 ,  H01L24/20 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2223/6616 ,  H01L2223/6677

摘要： This application relates to a device for signal transmission (e.g., radio frequency transmission) and a method for forming the device. For example, the method includes: depositing an insulating layer that includes polybenzobisoxazole (PBO) on a carrier; forming a backside layer including polyimide (PI) over the adhesive layer; forming a die-attach film (DAF) over the backside layer; forming one or more through-insulator via (TIV)-wall structures and one or more TIV-grating structures on the second backside layer; placing a die, such as a radio frequency (RF) integrated circuit (IC) die, on the DAF; encapsulating the die, the one or more TIV-wall structures, and the one or more TIV-grating structures, with a molding compound to form an antenna package including one or more antenna regions; and forming a redistribution layer (RDL) structure on the encapsulated package. The RDL structure can include one or more antenna structures coupled to the die. Each of the one or more antenna structures can be positioned over the one or more antenna regions.

公开(公告)号：US11791321B2

公开(公告)日：2023-10-17

申请号：US17580047

申请日：2022-01-20

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Tae-Young Lee ,  Dongok Kwak ,  Boseong Kim ,  Sang Sub Song ,  Joonyoung Oh

IPC分类号： H01L23/538 ,  H01L25/10 ,  H01L23/552 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L25/00 ,  H01L23/31

CPC分类号： H01L25/105 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/214 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06537 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2225/1035 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2924/3025

摘要： A method of fabricating a semiconductor package includes preparing a panel package including a redistribution substrate, a connection substrate and a plurality of lower semiconductor chips; sawing the panel package to form a plurality of separated strip packages each of which includes the sawed redistribution substrate, at least two of the lower semiconductor chips, and the sawed connection substrate; and providing a plurality of upper semiconductor chips on one of the strip packages to electrically connect the upper semiconductor chips to the sawed connection substrate.

公开(公告)号：US11791300B2

公开(公告)日：2023-10-17

申请号：US17135161

申请日：2020-12-28

申请人： SILICONWARE PRECISION INDUSTRIES CO., LTD.

发明人： Fang-Lin Tsai ,  Chia-Yu Kuo ,  Pei-Geng Weng ,  Wei-Son Tsai ,  Yih-Jenn Jiang

IPC分类号： H01L23/31 ,  H01L23/00

CPC分类号： H01L24/20 ,  H01L23/3157 ,  H01L2224/211 ,  H01L2224/2101 ,  H01L2224/214 ,  H01L2224/2105 ,  H01L2924/3511

摘要： An electronic package is provided, where a circuit layer and a metal layer having a plurality of openings are formed on a dielectric layer of a circuit portion to reduce the area ratio of the metal layer to the dielectric layer, so as to reduce stress concentration and prevent warping of the electronic package.