公开(公告)号：US09990289B2

公开(公告)日：2018-06-05

申请号：US14491296

申请日：2014-09-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Gabriel H. Loh ,  Derek R. Hower ,  Shuai Che

IPC: G06F12/08 ,  G06F12/0815 ,  G06F12/0864 ,  G06F12/0891

CPC classification number: G06F12/0815 ,  G06F12/0864 ,  G06F12/0891 ,  Y02D10/13

Abstract: A processing system having a multilevel cache hierarchy employs techniques for repurposing dead cache blocks so as to use otherwise wasted space in a cache hierarchy employing a write-back scheme. For a cache line containing invalid data with a valid tag, the valid tag is maintained for cache coherence purposes or otherwise, resulting in a valid tag for a dead cache block. A cache controller repurposes the dead cache block by storing any of a variety of new data at the dead cache block, while storing the new tag in a tag entry of a dead block tag way with an identifier indicating the location of the new data.

公开(公告)号：US20170277634A1

公开(公告)日：2017-09-28

申请号：US15081379

申请日：2016-03-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Arkaprava Basu ,  Mark H. Oskin ,  Gabriel H. Loh ,  Andrew G. Kegel ,  David S. Christie ,  Kevin J. McGrath

IPC: G06F12/08 ,  G06F12/10

CPC classification number: G06F12/1027 ,  G06F12/0811 ,  G06F2212/1024 ,  G06F2212/683 ,  G06F2212/684

Abstract: The described embodiments include a computing device with two or more translation lookaside buffers (TLB) that performs operations for handling entries in the TLBs. During operation, the computing device maintains lease values for entries in the TLBs, the lease values representing times until leases for the entries expire, wherein a given entry in the TLB is invalid when the associated lease has expired. The computing device uses the lease value to control operations that are allowed to be performed using information from the entries in the TLBs. In addition, the computing device maintains, in a page table, longest lease values for page table entries indicating when corresponding longest leases for entries in TLBs expire. The longest lease values are used to determine when and if a TLB shootdown is to be performed.

公开(公告)号：US20170177492A1

公开(公告)日：2017-06-22

申请号：US14973448

申请日：2015-12-17

Applicant: Advanced Micro Devices, Inc.

Inventor： Gabriel H. Loh

IPC: G06F12/08

CPC classification number: G06F12/0897 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0846 ,  G06F12/0895 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/502 ,  G06F2212/601 ,  G06F2212/604

Abstract: Systems, apparatuses, and methods for implementing a hybrid cache. A processor may include a hybrid L2/L3 cache which allows the processor to dynamically adjust a size of the L2 cache and a size of the L3 cache. In some embodiments, the processor may be a multi-core processor and there may be a single cache partitioned into a logical L2 cache and a logical L3 cache for use by the cores. In one embodiment, the processor may track the cache hit rates of the logical L2 and L3 caches and adjust the sizes of the logical L2 and L3 cache based on the cache hit rates. In another embodiment, the processor may adjust the sizes of the logical L2 and L3 caches based on which application is currently being executed by the processor.

公开(公告)号：US09489321B2

公开(公告)日：2016-11-08

申请号：US13917033

申请日：2013-06-13

Applicant: Advanced Micro Devices, Inc.

Inventor： James M. O'Connor ,  Niladrish Chatterjee ,  Nuwan S. Jayasena ,  Gabriel H. Loh

IPC: G06F13/16

CPC classification number: G06F13/1626 ,  G06F13/161 ,  G06F13/1694

Abstract: A memory accessing agent includes a memory access generating circuit and a memory controller. The memory access generating circuit is adapted to generate multiple memory accesses in a first ordered arrangement. The memory controller is coupled to the memory access generating circuit and has an output port, for providing the multiple memory accesses to the output port in a second ordered arrangement based on the memory accesses and characteristics of an external memory. The memory controller determines the second ordered arrangement by calculating an efficient row burst value and interrupting multiple row-hit requests to schedule a row-miss request based on the efficient row burst value.

Abstract translation: 存储器访问代理包括存储器访问生成电路和存储器控制器。 存储器访问生成电路适于以第一有序布置生成多个存储器访问。 存储器控制器耦合到存储器存取产生电路，并且具有输出端口，用于基于存储器访问和外部存储器的特性以第二有序布置提供对输出端口的多个存储器访问。 存储器控制器通过计算有效的行脉冲串值和中断多个行命中请求来基于有效的行脉冲串值来调度行错请求来确定第二排序。

公开(公告)号：US09344091B2

公开(公告)日：2016-05-17

申请号：US14551147

申请日：2014-11-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Nuwan S. Jayasena ,  Michael J. Schulte ,  Gabriel H. Loh ,  Michael Ignatowski

IPC: H03K19/177 ,  G11C7/00 ,  G06F15/78 ,  G06F13/16 ,  G06F11/10 ,  G06F13/42 ,  G11C7/10 ,  G11C29/00

CPC classification number: H03K19/1776 ,  G06F11/1004 ,  G06F13/1668 ,  G06F13/4234 ,  G06F15/7867 ,  G11C7/1006 ,  G11C7/1048 ,  G11C29/70 ,  H01L2224/16227 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H03K19/17776 ,  Y02D10/14 ,  Y02D10/151

Abstract: A die-stacked memory device incorporates a reconfigurable logic device to provide implementation flexibility in performing various data manipulation operations and other memory operations that use data stored in the die-stacked memory device or that result in data that is to be stored in the die-stacked memory device. One or more configuration files representing corresponding logic configurations for the reconfigurable logic device can be stored in a configuration store at the die-stacked memory device, and a configuration controller can program a reconfigurable logic fabric of the reconfigurable logic device using a selected one of the configuration files. Due to the integration of the logic dies and the memory dies, the reconfigurable logic device can perform various data manipulation operations with higher bandwidth and lower latency and power consumption compared to devices external to the die-stacked memory device.

Abstract translation: 芯片堆叠的存储器件包括可重构逻辑器件，以在执行各种数据操作操作和使用存储在管芯堆叠的存储器件中的数据的其他存储器操作中提供实现灵活性，或者导致要存储在管芯堆叠存储器件中的数据。 堆叠式存储设备。 代表可重配置逻辑器件的相应逻辑配置的一个或多个配置文件可被存储在管芯堆叠的存储器件的配置存储器中，并且配置控制器可使用所选择的一个存储器件对可重新配置的逻辑器件进行编程 配置文件。 由于逻辑管芯和存储器管芯的集成，与可堆叠存储器件外部的器件相比，可重构逻辑器件可以执行具有更高带宽和更低延迟和功耗的各种数据操作操作。

公开(公告)号：US20160055100A1

公开(公告)日：2016-02-25

申请号：US14463647

申请日：2014-08-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Gabriel H. Loh

IPC: G06F12/12 ,  G06F12/08

CPC classification number: G06F12/128 ,  G06F12/126 ,  Y02D10/13

Abstract: A processing system having multilevel cache employs techniques for identifying and selecting valid candidate cache lines for eviction from a lower level cache of an inclusive cache hierarchy, so as to reduce invalidations resulting from an eviction of a cache line in a lower level cache that also resides in a higher level cache. In response to an eviction trigger for a lower level cache, a cache controller identifies candidate cache lines for eviction from the cache lines residing in the lower level cache based on the replacement policy. The cache controller uses residency metadata to identify the candidate cache line as a valid candidate if it does not also reside in the higher cache and as an invalid candidate if it does reside in the higher cache. The cache controller prevents eviction of invalid candidates, so as to avoid unnecessary invalidations in the higher cache while maintaining inclusiveness.

Abstract translation: 具有多级高速缓存的处理系统采用用于识别和选择用于从包含高速缓存层级的较低级高速缓存驱逐的有效候选高速缓存线的技术，以便减少由于也驻留的较低级高速缓存中的高速缓存行的驱逐而导致的无效 在更高级别的缓存中。 响应于较低级别高速缓存的驱逐触发器，高速缓存控制器基于替换策略识别驻留在较低级别高速缓存中的高速缓存行的用于逐出的候选高速缓存行。 高速缓存控制器使用驻留元数据将候选高速缓存行识别为有效候选，如果它也不驻留在较高的高速缓存中，并且如果它驻留在较高的高速缓存中则为无效候选。 高速缓存控制器防止驱逐无效候选，以避免在高速缓存中不必要的无效，同时保持包容性。

公开(公告)号：US09218204B2

公开(公告)日：2015-12-22

申请号：US13725724

申请日：2012-12-21

Applicant: Advanced Micro Devices, Inc.

Inventor： James M. O'Connor ,  Michael J. Schulte ,  Nuwan S. Jayasena ,  Gabriel H. Loh

IPC: G06F9/50 ,  G06F9/52

CPC classification number: G06F9/50 ,  G06F9/526 ,  G06F2209/521 ,  G06F2209/522

Abstract: A system includes an atomic processing engine (APE) coupled to an interconnect. The interconnect is to couple to one or more processor cores. The APE receives a plurality of commands from the one or more processor cores through the interconnect. In response to a first command, the APE performs a first plurality of operations associated with the first command. The first plurality of operations references multiple memory locations, at least one of which is shared between two or more threads executed by the one or more processor cores.

Abstract translation: 系统包括耦合到互连的原子处理引擎（APE）。 互连将耦合到一个或多个处理器内核。 APE通过互连从一个或多个处理器核接收多个命令。 响应于第一命令，APE执行与第一命令相关联的第一多个操作。 第一组多个操作引用多个存储器位置，其中至少一个在一个或多个处理器核心执行的两个或多个线程之间共享。

公开(公告)号：US09106260B2

公开(公告)日：2015-08-11

申请号：US13720504

申请日：2012-12-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： James M. O'Connor ,  Vilas K. Sridharan ,  Gabriel H. Loh

IPC: H03M13/11 ,  G06F11/00 ,  H03M13/53 ,  H03M13/05

CPC classification number: H03M13/11 ,  G06F11/00 ,  G06F11/1048 ,  H03M13/05

Abstract: A processor system as presented herein includes a processor core, cache memory coupled to the processor core, a memory controller coupled to the cache memory, and a system memory component coupled to the memory controller. The system memory component includes a plurality of independent memory channels configured to store data blocks, wherein the memory controller controls the storing of parity bits in at least one of the plurality of independent memory channels. In some implementations, the system memory is realized as a die-stacked memory component.

Abstract translation: 如本文所述的处理器系统包括处理器核心，耦合到处理器核心的高速缓存存储器，耦合到高速缓冲存储器的存储器控​​制器以及耦合到存储器控制器的系统存储器组件。 系统存储器组件包括被配置为存储数据块的多个独立存储器通道，其中存储器控制器控制在多个独立存储器通道中的至少一个中存储奇偶校验位。 在一些实现中，系统存储器被实现为管芯堆叠的存储器组件。

公开(公告)号：US09053039B2

公开(公告)日：2015-06-09

申请号：US13724867

申请日：2012-12-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Matthew R. Poremba ,  Gabriel H. Loh

IPC: G06F12/08

CPC classification number: G06F12/0893 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0862 ,  Y02D10/13

Abstract: Data caching methods and systems are provided. The data cache method loads data into an installation cache and a cache (simultaneously or serially) and returns data from the installation cache when the data has not completely loaded into the cache. The data cache system includes a processor, a memory coupled to the processor, a cache coupled to the processor and the memory and an installation cache coupled to the processor and the memory. The system is configured to load data from the memory into the installation cache and the cache (simultaneously or serially) and return data from the installation cache to the processor when the data has not completely loaded into the cache.

Abstract translation: 提供数据缓存方法和系统。 数据高速缓存方法将数据加载到安装高速缓存和高速缓存（同时或连续）中，并在数据尚未完全加载到高速缓存中时从安装高速缓存返回数据。 数据缓存系统包括处理器，耦合到处理器的存储器，耦合到处理器和存储器的高速缓存以及耦合到处理器和存储器的安装高速缓存。 该系统被配置为当数据尚未完全加载到高速缓存中时，将数据从存储器加载到安装高速缓存和高速缓存（同时或串行）中，并将数据从安装高速缓存返回到处理器。

公开(公告)号：US08984368B2

公开(公告)日：2015-03-17

申请号：US13649745

申请日：2012-10-11

Applicant: Advanced Micro Devices, Inc.

Inventor： Gabriel H. Loh ,  Vilas K. Sridharan

IPC: G11C29/00 ,  G06F11/10

CPC classification number: G06F11/1044

Abstract: An integrated circuit includes a memory having an address space and a memory controller coupled to the memory for accessing the address space in response to received memory accesses. The memory controller further accesses a plurality of data elements in a first portion of the address space, and reliability data corresponding to the plurality of data elements in a second portion of the address space.

Abstract translation: 集成电路包括具有地址空间的存储器和耦合到存储器的存储器控​​制器，用于响应于接收到的存储器访问来访问地址空间。 存储器控制器还访问地址空间的第一部分中的多个数据元素以及与地址空间的第二部分中的多个数据元素相对应的可靠性数据。