公开(公告)号：US6094058A

公开(公告)日：2000-07-25

申请号：US949383

申请日：1997-10-14

Applicant: David R. Hembree ,  Warren M Farnworth ,  Alan G. Wood ,  Salman Akram

Inventor： David R. Hembree ,  Warren M Farnworth ,  Alan G. Wood ,  Salman Akram

IPC: G01R1/04 ,  G01R1/067 ,  G01R1/073 ,  G01R3/00 ,  G01R31/28 ,  H01L21/60 ,  H01L21/66 ,  H01L21/68 ,  H01L23/13 ,  H01L23/498 ,  H05K3/00 ,  H05K3/40 ,  H05K3/42

CPC classification number: H01L23/49838 ,  G01R1/0433 ,  G01R1/0466 ,  G01R1/0483 ,  H01L21/6835 ,  H01L22/20 ,  H01L23/13 ,  H01L23/49816 ,  H01L24/80 ,  H05K3/4007 ,  G01R1/0735 ,  G01R3/00 ,  G01R31/2863 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15174 ,  H05K2201/0133 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/0307 ,  H05K2203/0723 ,  H05K3/0058 ,  H05K3/0067 ,  H05K3/423

Abstract: A temporary package for a semiconductor die is provided. The temporary package has an outline and external contact configuration that are the same as a conventional plastic or ceramic semiconductor package. The temporary package can be used for burn-in testing of the die using standard equipment. The die can then be removed from the package and certified as a known good die. The package includes a base, an interconnect and a force applying mechanism. The package base includes external contacts formed in a dense array, such as a land grid array (LGA), a pin grid array (PGA), a bumped grid array (BGA) or a perimeter array. The package base can be formed of ceramic or plastic with internal conductive lines using a ceramic lamination process, a 3-D molding process or a Cerdip formation process.

公开(公告)号：US6072321A

公开(公告)日：2000-06-06

申请号：US972088

申请日：1997-11-17

Applicant: Salman Akram ,  David R. Hembree ,  Alan G. Wood

Inventor： Salman Akram ,  David R. Hembree ,  Alan G. Wood

IPC: G01R31/02

CPC classification number: G01R31/02 ,  Y10T29/49222

Abstract: A probe card for testing semiconductor dice contained on a wafer and a method for fabricating the probe card are provided. The probe card includes a substrate preferably formed of silicon, and having a pattern of contact members corresponding to a pattern of test pads on the wafer. Each contact member is formed integrally with the substrate and includes a projection formed as an elongated blade adapted to penetrate into a corresponding test pad to a limited penetration depth. In addition, a cavity and a flexible membrane are formed in the substrate subjacent to the contact members to permit flexure of the contact members. Fluid or gas pressure can be introduced into the cavity through flow passages formed in the substrate.

Abstract translation: 提供了用于测试包含在晶片上的半导体晶片的探针卡和用于制造探针卡的方法。 探针卡包括优选由硅形成并且具有对应于晶片上的测试焊盘图案的接触构件图案的衬底。 每个接触构件与衬底一体地形成，并且包括形成为细长刀片的突起，其适于将相应的试验垫渗透到有限的穿透深度。 此外，在与接触构件相邻的衬底中形成空腔和柔性膜以允许接触构件的挠曲。 流体或气体压力可以通过形成在基底中的流动通道引入空腔。

公开(公告)号：US6072236A

公开(公告)日：2000-06-06

申请号：US612059

申请日：1996-03-07

Applicant: Salman Akram ,  David R. Hembree ,  Warren M. Farnworth

Inventor： Salman Akram ,  David R. Hembree ,  Warren M. Farnworth

IPC: H01L21/60 ,  H01L23/485 ,  H01L23/04 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/13 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/1148 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/13339 ,  H01L2224/16237 ,  H01L2924/0001 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043

Abstract: A chip scale package comprised of a semiconductor die having a silicon blank laminated to its active surface. The bond pads of the die are accessed through apertures micromachined through the blank. The package may be employed with wire bonds, or solder or other conductive bumps may be placed in the blank apertures for flip-chip applications. Further, the package may be employed to reroute external connections of the die to other locations, such as a centralized ball grid array or in an edge-connect arrangement for direct or discrete die connect (DDC) to a carrier. It is preferred that the chip scale package be formed at the wafer level, as one of a multitude of packages so formed with a wafer-level blank, and that the entire wafer be burned-in and tested to identify the known good die (KGD) before the wafer laminate is separated into individual packages.

公开(公告)号：US6064194A

公开(公告)日：2000-05-16

申请号：US767700

申请日：1996-12-17

Applicant: Warren M. Farnworth ,  Jennifer L. Folaron ,  Robert J. Folaron ,  David R. Hembree ,  John O. Jacobson ,  Jay C. Nelson ,  Lelan D. Warren

Inventor： Warren M. Farnworth ,  Jennifer L. Folaron ,  Robert J. Folaron ,  David R. Hembree ,  John O. Jacobson ,  Jay C. Nelson ,  Lelan D. Warren

IPC: G01R31/26 ,  G01R31/28 ,  G01R31/311 ,  H01L21/00 ,  H01L21/60 ,  H01L21/66 ,  H01L21/68 ,  H05K13/08 ,  G01R31/02

CPC classification number: H01L21/67276 ,  G01R31/2851 ,  G01R31/2886 ,  G01R31/2893 ,  H01L21/67126 ,  H01L21/67242 ,  H01L21/67259 ,  H01L21/681 ,  H01L24/74 ,  H05K13/08 ,  G01R31/311 ,  H01L2924/12042 ,  H01L2924/14 ,  Y10T29/49004 ,  Y10T29/49131 ,  Y10T29/53174 ,  Y10T29/53178

Abstract: An apparatus for automatically positioning electronic dice within temporary packages to enable continuity testing between the dice bond pads and the temporary package electrical interconnects is provided. The apparatus includes a robot having a programmable robot arm with a gripper assembly, die and lid feeder stations, a die inverter, and a plurality of cameras. The cameras take several pictures of the die and temporary packages to precisely align the die bond pads with the temporary package electrical interconnects. A predetermined assembly position is located along a conveyor that conveys a carrier between a first position, corresponding to an inlet, and a second position, corresponding to an outlet. The die, a restraining device and temporary package are assembled at the predetermined assembly position and tested for continuity therebetween. The apparatus further includes a fifth camera which locates the die at a wafer handler. The apparatus has a control mechanism including a microprocessor and program routines that selectively control the robot arm (i) to move the gripper assembly to the lid feeder station to pick up a lid, (ii) to move the gripper assembly along with the lid to pick up the die, (iii) to move the gripper assembly along with the lid and the die to a position to be photographed by the fine die camera, and (iv) to move the lid and the die to the predetermined assembly position located along the conveyor. The method and apparatus may also be used for disassembly.

Abstract translation: 提供了一种用于将电子骰子自动定位在临时包装内的装置，以实现骰子接合焊盘和临时封装电互连之间的连续性测试。 该装置包括具有可编程机器人臂的机器人，其具有夹持器组件，模具和盖子馈送站，模具反相器和多个相机。 相机拍摄模具和临时包装的几张照片，以便将芯片接合焊盘与临时封装电气互连精确对准。 预定的组装位置沿着输送机定位，该输送器在对应于出口的第一位置（对应于入口）和第二位置之间输送载体。 模具，约束装置和临时包装组装在预定的组装位置，并测试其间的连续性。 该设备还包括一个将晶片定位在晶片处理器上的第五相机。 该装置具有包括微处理器和程序程序的控制机构，该程序程序选择性地控制机器人手臂（i）将夹持器组件移动到盖子馈送站以拾取盖子，（ii）将夹持器组件与盖子一起移动到 拾取模具，（iii）将夹具组合件与盖和模具一起移动到由精细模具相机拍摄的位置，以及（iv）将盖子和模具移动到沿着预定的组装位置 输送机 该方法和装置也可以用于拆卸。

公开(公告)号：US6045026A

公开(公告)日：2000-04-04

申请号：US27690

申请日：1998-02-23

Applicant: David R. Hembree ,  Michael E. Hess ,  John O. Jacobson ,  Warren M. Farnworth ,  Alan G. Wood

Inventor： David R. Hembree ,  Michael E. Hess ,  John O. Jacobson ,  Warren M. Farnworth ,  Alan G. Wood

IPC: B23K20/10

CPC classification number: B23K20/10 ,  B23K2201/38

Abstract: A machine and method for bonding puncture-type conductive contact members of an interconnect to the bond pads of a bare semiconductor die includes the use of one or two ultrasonic vibrators mounted to vibrate one or both of the die and interconnect. A short axial linear burst of ultrasonic energy enables the contact members to pierce hard oxide layers on the surfaces of the bond pads at a much lower compressive force and rapidly achieve full penetration depth.

公开(公告)号：US6040702A

公开(公告)日：2000-03-21

申请号：US888075

申请日：1997-07-03

Applicant: David R. Hembree ,  Warren M. Farnworth ,  Alan G. Wood ,  Derek Gochnour ,  Salman Akram

Inventor： David R. Hembree ,  Warren M. Farnworth ,  Alan G. Wood ,  Derek Gochnour ,  Salman Akram

IPC: G01R31/26 ,  G01R1/04 ,  G01R1/073 ,  G01R31/02 ,  H01L21/66 ,  H01L23/12 ,  H01L23/32 ,  H01R13/631 ,  H01R13/642 ,  H01R33/76

CPC classification number: G01R1/0483 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/81385 ,  H01L2924/01021 ,  H01L2924/01087 ,  H01L2924/09701

Abstract: A semiconductor carrier and system for testing bumped semiconductor components, such as dice and packages, having contact bumps are provided. The carrier includes a base, an interconnect, and a force applying mechanism. The interconnect includes patterns of contact members adapted to electrically contact the contact bumps. The interconnect can include a substrate having contact members formed as recesses, or as projections, covered with conductive layers. Alternately, the interconnect can be a multi layered tape bonded directly to a base of the carrier. In addition to providing electrical connections, the contact members perform an alignment function by self centering the contact bumps within the contact members. The carrier can also include an alignment member configured to align the components with the interconnect. The system can include the carrier, a socket, and a testing apparatus such as a burn-in board in electrical communication with test circuitry.

Abstract translation: 提供了一种半导体载体和系统，用于测试具有接触凸块的凸起的半导体部件，例如芯片和封装。 载体包括基底，互连和力施加机构。 互连包括适于电接触接触凸块的接触构件的图案。 互连可以包括具有形成为凹陷的接触构件的衬底，或者作为突出部的覆盖有导电层的衬底。 或者，互连可以是直接结合到载体的基底的多层带。 除了提供电连接之外，接触构件通过使接触构件内的接触凸块自对中来执行对准功能。 载体还可以包括配置成将部件与互连对准的对准部件。 该系统可以包括载体，插座和诸如与测试电路电连接的老化板的测试装置。

公开(公告)号：US6016060A

公开(公告)日：2000-01-18

申请号：US823490

申请日：1997-03-25

Applicant: Salman Akram ,  Warren M. Farnworth ,  Alan G. Wood ,  David R. Hembree

Inventor： Salman Akram ,  Warren M. Farnworth ,  Alan G. Wood ,  David R. Hembree

IPC: G01R1/04 ,  G01R1/067 ,  G01R1/073 ,  G01R31/28 ,  G01R31/26

CPC classification number: G01R1/0466

Abstract: A method, apparatus and system for establishing temporary electrical communication with semiconductor components having contact bumps are provided. The apparatus includes an interconnect having patterns of contact members adapted to electrically contact the contact bumps. Each contact member includes an array of one or more electrically conductive projections in electrical communication with an associated conductor. The projections form contact members for retaining individual contact bumps on the semiconductor components. The projections can be pillars having angled faces covered with a conductive layer. Alternately the projections can be a material deposited on the substrate, or can be microbumps formed on multi layered tape bonded to the substrate. The interconnect can be employed in a wafer level test system for testing dice contained on a wafer, or in a die level test system for testing bare bumped dice or bumped chip scale packages.

公开(公告)号：US5952840A

公开(公告)日：1999-09-14

申请号：US770942

申请日：1996-12-31

Applicant: Warren M. Farnworth ,  Salman Akram ,  Alan G. Wood ,  David R. Hembree ,  James M. Wark ,  John O. Jacobson

Inventor： Warren M. Farnworth ,  Salman Akram ,  Alan G. Wood ,  David R. Hembree ,  James M. Wark ,  John O. Jacobson

IPC: G01R1/04 ,  G01R31/28 ,  G01R31/02

CPC classification number: G01R1/0491 ,  G01R31/2886

Abstract: A method, apparatus and system for testing semiconductor wafers are provided. The method includes providing a wafer carrier to provide an electrical path for receiving and transmitting test signals to the wafer. The wafer carrier includes a base for retaining the wafer, and an interconnect having contact members configured to establish electrical communication with contact locations on the wafer. The wafer carrier can include one or more compressible spring members configured to bias the wafer and interconnect together in the assembled carrier. The wafer carrier can be assembled, with the wafer in alignment with the interconnect, using optical alignment techniques, and an assembly tool similar to aligner bonder tools used for flip chip bonding semiconductor dice. A system for use with the carrier can include a testing apparatus configured to apply test signals through the carrier to the wafer while the wafer is subjected to temperature cycling.

公开(公告)号：US5929647A

公开(公告)日：1999-07-27

申请号：US674473

申请日：1996-07-02

Applicant: Salman Akram ,  Alan G. Wood ,  David R. Hembree ,  Warren M. Farnworth

Inventor： Salman Akram ,  Alan G. Wood ,  David R. Hembree ,  Warren M. Farnworth

IPC: G01R1/04 ,  G01R31/28 ,  G01R1/073 ,  G01R31/02

CPC classification number: G01R31/2886 ,  G01R1/0483 ,  H01L2224/05553 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15151 ,  H01L2924/30107

Abstract: A method and carrier for testing semiconductor dice such as bare dice or chip scale packages are provided. The carrier includes a base for retaining a single die, an interconnect for establishing temporary electrical communication with the die, and a force applying mechanism for biasing the die and interconnect together. In an illustrative embodiment the base includes conductors arranged in a universal pattern adapted to electrically connect to different sized interconnects. Interconnects are thus interchangeable on a base for testing different types of dice using the same base. The conductors on the base can be formed on a planar active surface of the base or on a stepped active surface having different sized cavities for mounting different sized interconnects. In an alternate embodiment the carrier includes an interposer. In a first interposer embodiment, the interposer connects directly to external test circuitry and can be changed to accommodate different sized interconnects. In a second interposer embodiment, the interposer connects to conductors on the base and adapts the base for use with different sized interconnects.

Abstract translation: 提供了用于测试半导体裸片（例如裸裸片或芯片级封装）的方法和载体。 载体包括用于保持单个管芯的基座，用于建立与管芯的临时电连通的互连件，以及用于偏压管芯并互连在一起的施力机构。 在说明性实施例中，底座包括以适于电连接到不同尺寸的互连件的通用图案布置的导体。 因此，互连在基座上可以互换，用于使用相同的基底测试不同类型的骰子。 基底上的导体可以形成在基座的平面有源表面上或具有不同尺寸的空腔的阶梯式有源表面上，用于安装不同尺寸的互连件。 在替代实施例中，载体包括插入器。 在第一插入器实施例中，插入器直接连接到外部测试电路，并且可以改变以适应不同尺寸的互连。 在第二插入器实施例中，插入器连接到基座上的导体，并使基座适配于不同大小的互连使用。

公开(公告)号：US5869974A

公开(公告)日：1999-02-09

申请号：US625281

申请日：1996-04-01

Applicant: Salman Akram ,  David R. Hembree ,  Alan G. Wood

Inventor： Salman Akram ,  David R. Hembree ,  Alan G. Wood

IPC: G01R31/02

CPC classification number: G01R31/02 ,  Y10T29/49222

Abstract: A probe card for testing semiconductor dice contained on a wafer and a method for fabricating the probe card are provided. The probe card includes a substrate preferably formed of silicon, and having a pattern of contact members corresponding to a pattern of test pads on the wafer. Each contact member is formed integrally with the substrate and includes a projection formed as an elongated blade adapted to penetrate into a corresponding test pad to a limited penetration depth. In addition, a cavity and a flexible membrane are formed in the substrate subjacent to the contact members to permit flexure of the contact members. Fluid or gas pressure can be introduced into the cavity through flow passages formed in the substrate.

Abstract translation: 提供了用于测试包含在晶片上的半导体晶片的探针卡和用于制造探针卡的方法。 探针卡包括优选由硅形成并且具有对应于晶片上的测试焊盘图案的接触构件图案的衬底。 每个接触构件与衬底一体地形成，并且包括形成为细长刀片的突起，其适于将相应的试验垫渗透到有限的穿透深度。 此外，在与接触构件相邻的衬底中形成空腔和柔性膜以允许接触构件的挠曲。 流体或气体压力可以通过形成在基底中的流动通道引入空腔。