公开(公告)号：US07387717B2

公开(公告)日：2008-06-17

申请号：US10631726

申请日：2003-08-01

申请人： Junji Kunisawa ,  Mitsuko Odagaki ,  Natsuki Makino ,  Koji Mishima ,  Kenji Nakamura ,  Hiroaki Inoue ,  Norio Kimura ,  Tetsuo Matsuda ,  Hisashi Kaneko ,  Nobuo Hayasaka ,  Katsuya Okumura ,  Manabu Tsujimura ,  Toshiyuki Morita

发明人： Junji Kunisawa ,  Mitsuko Odagaki ,  Natsuki Makino ,  Koji Mishima ,  Kenji Nakamura ,  Hiroaki Inoue ,  Norio Kimura ,  Tetsuo Matsuda ,  Hisashi Kaneko ,  Nobuo Hayasaka ,  Katsuya Okumura ,  Manabu Tsujimura ,  Toshiyuki Morita

IPC分类号： C25D7/12

CPC分类号： H01L21/6719 ,  C25D7/123 ,  C25D17/001 ,  C25D17/12 ,  C25D17/14 ,  H01L21/2885 ,  H01L21/67046 ,  H01L21/67051 ,  H01L21/6708 ,  H01L21/6715 ,  H01L21/6723 ,  H01L21/76877 ,  H01L21/76879 ,  H01L2924/0002 ,  H05K3/423 ,  H01L2924/00

摘要： A plating method and apparatus for a substrate fills a metal, e.g., copper, into a fine interconnection pattern formed in a semiconductor substrate. The apparatus has a substrate holding portion 36 horizontally holding and rotating a substrate with its surface to be plated facing upward. A seal material 90 contacts a peripheral edge portion of the surface, sealing the portion in a watertight manner. A cathode electrode 88 passes an electric current upon contact with the substrate. A cathode portion 38 rotates integrally with the substrate holding portion 36. An electrode arm portion 30 is above the cathode portion 38 and movable horizontally and vertically and has an anode 98 face-down. Plating liquid is poured into a space between the surface to be plated and the anode 98 brought close to the surface to be plated. Thus, plating treatment and treatments incidental thereto can be performed by a single unit.

摘要翻译： 用于衬底的电镀方法和装置将诸如铜的金属填充到形成在半导体衬底中的精细互连图案中。 该装置具有基板保持部分36，其水平地保持并旋转基板，其表面被面向上。 密封材料90接触表面的周缘部分，以水密的方式密封该部分。 阴极电极88在与基板接触时通过电流。 阴极部38与基板保持部36一体地旋转。电极臂部30在阴极部38的上方，水平且垂直地移动，阳极98面朝下。 将电镀液注入被镀表面与接近待镀表面的阳极98之间的空间中。 因此，电镀处理和附带的处理可以通过单个单元进行。

公开(公告)号：US07344986B2

公开(公告)日：2008-03-18

申请号：US10482104

申请日：2002-11-06

申请人： Hiroaki Inoue ,  Xinming Wang ,  Moriji Matsumoto ,  Makoto Kanayama

发明人： Hiroaki Inoue ,  Xinming Wang ,  Moriji Matsumoto ,  Makoto Kanayama

IPC分类号： H01L21/4763

CPC分类号： H01L21/76849 ,  C23C18/48 ,  C25D3/58 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/7684 ,  H01L23/53238 ,  H01L23/53252 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to a plating solution useful for forming embedded interconnects by embedding a conductive material in fine recesses for interconnects provided in the surface of a substrate, such as a semiconductor substrate, or for forming a protective layer for protecting the surface of embedded interconnects, a semiconductor device manufactured by using the plating solution and a method for manufacturing the semiconductor device. The plating solution contains copper ions, metal ions of a metal, and the metal is capable of forming with copper a copper alloy in which the metal does not form a solid solution with copper, a complexing agent, and a reducing agent free from alkali metal.

摘要翻译： 本发明涉及一种用于通过将导电材料嵌入到设置在诸如半导体衬底的衬底的表面中的互连的精细凹槽中的用于形成嵌入式互连的电镀液，或用于形成用于保护嵌入式互连的表面的保护层 ，使用电镀液制造的半导体装置及其制造方法。 电镀溶液含有铜离子，金属的金属离子，金属能够与铜形成铜合金，其中金属不与铜形成固溶体，络合剂和不含碱金属的还原剂 。

公开(公告)号：US07279408B2

公开(公告)日：2007-10-09

申请号：US11254790

申请日：2005-10-21

申请人： Hiroaki Inoue ,  Norio Kimura ,  Xinming Wang ,  Moriji Matsumoto ,  Makoto Kanayama

发明人： Hiroaki Inoue ,  Norio Kimura ,  Xinming Wang ,  Moriji Matsumoto ,  Makoto Kanayama

IPC分类号： H01L21/44

CPC分类号： H01L21/76843 ,  C23C18/1608 ,  C23C18/1632 ,  C23C18/1653 ,  C23C18/32 ,  C23C18/48 ,  C23C18/50 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/3212 ,  H01L21/7684 ,  H01L21/76849 ,  H01L21/76864 ,  H01L21/76874 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53238 ,  H01L23/53252 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to a semiconductor device and a method for manufacturing the same. The semiconductor device has an embedded interconnect structure in which an electric conductor, such as copper or silver, is embedded in fine recesses formed in a surface of a semiconductor substrate, and also has a protective film formed on surfaces of exposed interconnects that define the interconnect structure, to protect the interconnects. The protective film has a flattened surface.

摘要翻译： 半导体器件及其制造方法技术领域本发明涉及半导体器件及其制造方法。 半导体器件具有嵌入式互连结构，其中诸如铜或银的电导体嵌入形成在半导体衬底的表面中的细小凹槽中，并且还具有形成在暴露的互连件的表面上的保护膜，所述互连限定了互连 结构，保护互连。 保护膜具有平坦的表面。

公开(公告)号：US20070097055A1

公开(公告)日：2007-05-03

申请号：US11507497

申请日：2006-08-22

申请人： Satoshi Takamura ,  Hidetoshi Okazaki ,  Hiroaki Inoue

发明人： Satoshi Takamura ,  Hidetoshi Okazaki ,  Hiroaki Inoue

IPC分类号： G09G3/36

CPC分类号： G09G3/3622 ,  G09G3/3614 ,  G09G2330/02 ,  G09G2330/025

摘要： An apparatus includes a polarity reversing section which generates a polarity reversing signal for the liquid crystal drive voltage; a liquid crystal driver which reverses the polarity of the liquid crystal drive voltage based on the polarity reversing signal to drive the liquid crystal display panel; a warning signal generation section which generates a warning signal indicating the polarity reverse before the polarity of the liquid crystal drive voltage is reversed; and a regulator section which controls a supply of the liquid crystal drive voltage in accordance with the warning signal.

摘要翻译： 一种装置包括：极性反转部，其生成用于液晶驱动电压的极性反转信号; 液晶驱动器，其根据极性反转信号反转液晶驱动电压的极性，驱动液晶显示面板; 警告信号生成部，其在液晶驱动电压的极性反转之前生成表示极性反转的警告信号; 以及调节器部，其根据所述警告信号控制所述液晶驱动电压的供给。

公开(公告)号：US07208074B2

公开(公告)日：2007-04-24

申请号：US10742390

申请日：2003-12-22

申请人： Koji Mishima ,  Junji Kunisawa ,  Natsuki Makino ,  Norio Kimura ,  Hiroaki Inoue ,  Kenji Nakamura ,  Moriji Matsumoto ,  Takahiro Nanjo ,  Mitsuko Odagaki

发明人： Koji Mishima ,  Junji Kunisawa ,  Natsuki Makino ,  Norio Kimura ,  Hiroaki Inoue ,  Kenji Nakamura ,  Moriji Matsumoto ,  Takahiro Nanjo ,  Mitsuko Odagaki

IPC分类号： C25C28/00 ,  C25D5/10

CPC分类号： H01L21/67109 ,  C25D7/123 ,  C25D17/001 ,  H01L21/2885 ,  H01L21/67778 ,  H01L21/681

摘要： A substrate processing apparatus fills a metal such as copper or the like in fine interconnection patterns or trenches defined in a semiconductor substrate. The substrate processing apparatus has a loading/unloading unit for placing a substrate cassette to allow a substrate to be loaded and unloaded, a substrate treating unit for treating a substrate, and a transfer robot for transferring a substrate between the loading/unloading unit and the substrate treating unit. The loading/unloading unit, the substrate treating unit, and the transfer robot are installed in a single facility. The loading/unloading unit has a rotary table which is horizontally rotatable for positioning the substrate cassette in a position to detect the substrate cassette placed in the loading/unloading unit and to remove the substrate from the substrate cassette with the transfer robot.

摘要翻译： 基板处理装置以限定在半导体基板中的精细互连图案或沟槽中填充诸如铜等的金属。 基板处理装置具有用于放置基板盒以装载和卸载基板的装载/卸载单元，用于处理基板的基板处理单元，以及用于在装载/卸载单元和卸载单元之间传送基板的传送机器人 底物处理单元。 装载/卸载单元，基板处理单元和传送机器人安装在单个设施中。 装载/卸载单元具有可水平旋转的旋转台​​，用于将基板盒定位在检测装载/卸载单元中的基板盒的位置，并用传送机器人从基板盒移除基板。

公开(公告)号：US06861704B2

公开(公告)日：2005-03-01

申请号：US10663705

申请日：2003-09-17

申请人： Hitoshi Asada ,  Hiroaki Inoue

发明人： Hitoshi Asada ,  Hiroaki Inoue

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/417 ,  H01L29/49 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/0847 ,  H01L21/823418 ,  H01L21/823468 ,  H01L29/41775 ,  H01L29/4933 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7835

摘要： The semiconductor device comprises a gate electrode 26 formed on a semiconductor substrate 10, a source region 45a having a lightly doped source region 42a and a heavily doped source region 44a, a drain region 45b having a lightly doped drain region 42b and a heavily doped drain region 44b, a first silicide layer 40c formed on the source region, a second silicide layer 40d formed on the drain region, a first conductor plug 54 connected to the first silcide layer and a second conductor plug 54 connected to the second silicide layer. The heavily doped drain region is formed in the region of the lightly doped region except the peripheral region, and the second silicide layer is formed in the region of the heavily doped drain region except the peripheral region. Thus, the concentration of the electric fields on the drain region can be mitigated when voltages are applied to the drain region. Thus, even with the silicide layer formed on the source/drain region, sufficiently high withstand voltages of the high withstand voltage transistor can be ensured. Furthermore, the drain region alone has the above-described structure, whereby the increase of the source-drain electric resistance can be prevented while high withstand voltages can be ensured.

摘要翻译： 半导体器件包括形成在半导体衬底10上的栅电极26，具有轻掺杂源极区域42a和重掺杂源极区域44a的源极区域45a，具有轻掺杂漏极区域42b的漏极区域45b和重掺杂漏极 区域44b，形成在源极区上的第一硅化物层40c，形成在漏极区上的第二硅化物层40d，连接到第一硅化物层的第一导体插塞54和连接到第二硅化物层的第二导体插塞54。 重掺杂漏极区域形成在除了外围区域之外的轻掺杂区域的区域中，并且第二硅化物层形成在除了周边区域之外的重掺杂漏极区域的区域中。 因此，当向漏极区域施加电压时，可以减轻漏极区域上的电场的浓度。 因此，即使在源极/漏极区域上形成硅化物层，也可以确保高耐压晶体管的足够高的耐受电压。 此外，单独的漏极区域具有上述结构，由此可以防止源极 - 漏极电阻的增加，同时可以确保高耐受电压。

公开(公告)号：US20050029669A1

公开(公告)日：2005-02-10

申请号：US10893244

申请日：2004-07-19

申请人： Hiroaki Inoue ,  Akira Susaki

发明人： Hiroaki Inoue ,  Akira Susaki

IPC分类号： C23C18/16 ,  C25D7/12 ,  H01L21/288 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48 ,  H01L23/52

CPC分类号： H01L21/76885 ,  H01L21/76852 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53252 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device including a highly reliable multi-level interconnect structure having a low effective dielectric constant and which can be easily manufactured with a relatively inexpensive process, and a method for manufacturing the semiconductor device. The semiconductor device includes a lower-level interconnect and an upper-level interconnect, each surrounded by a barrier layer, and a via plug surrounded by a barrier layer and electrically connecting the lower-level interconnect and the upper-level interconnect.

摘要翻译： 一种半导体器件，包括具有低有效介电常数的高可靠性多电平互连结构，并且可以以相对便宜的工艺容易地制造，以及半导体器件的制造方法。 该半导体器件包括一个下层互连和一个上层互连，每一个都被一个阻挡层包围，一个由阻挡层包围并通过电气连接下层互连和上层互连的通孔。

公开(公告)号：US06717189B2

公开(公告)日：2004-04-06

申请号：US09880005

申请日：2001-06-14

申请人： Hiroaki Inoue ,  Kenji Nakamura ,  Moriji Matsumoto

发明人： Hiroaki Inoue ,  Kenji Nakamura ,  Moriji Matsumoto

IPC分类号： H01L31072

CPC分类号： H01L21/288 ,  C23C18/1607 ,  C23C18/1635 ,  C23C18/34 ,  C23C18/50 ,  H01L21/02063 ,  H01L21/0209 ,  H01L21/6723 ,  H01L21/76843 ,  H01L21/76849 ,  Y10S428/901 ,  Y10T428/24917

摘要： The present invention relates to an electroless-plating liquid useful for forming a protective film for selectively protecting surface of exposed interconnects of a semiconductor device which has an embedded interconnect structure formed by an electric conductor, such as copper or silver, embedded in fine recesses for interconnects formed in a surface of a semiconductor substrate, and also to a semiconductor device in which surfaces of exposed interconnects are selectively protected with a protective film. The electroless-plating liquid contains cobalt ions, a complexing agent and a reducing agent containing no alkali metal.

公开(公告)号：US06706422B2

公开(公告)日：2004-03-16

申请号：US09994834

申请日：2001-11-28

申请人： Hiroaki Inoue ,  Kenji Nakamura ,  Moriji Matsumoto ,  Hirokazu Ezawa ,  Masahiro Miyata ,  Manabu Tsujimura

发明人： Hiroaki Inoue ,  Kenji Nakamura ,  Moriji Matsumoto ,  Hirokazu Ezawa ,  Masahiro Miyata ,  Manabu Tsujimura

IPC分类号： B32B1504

CPC分类号： C23C18/50 ,  C23C18/34 ,  Y10T428/12576 ,  Y10T428/12896 ,  Y10T428/12903 ,  Y10T428/12944 ,  Y10T428/265

摘要： There is provided an electroless Ni—B plating liquid for forming, a Ni—B alloy film on at least part of the interconnects of an electronic device having an embedded interconnect structure, the electroless Ni—B plating liquid comprising nickel ions, a complexing agent for nickel ions, a reducing agent for nickel ions, and ammonums (NH4+). The electroless Ni—B plating liquid can lower the boron content of the resulting plated film without increasing the plating rate and form a Ni—B alloy film having an FCC crystalline structure.

摘要翻译： 提供了一种无电Ni-B电镀液，用于在具有嵌入式互连结构的电子器件的至少一部分互连上形成Ni-B合金膜，包含镍离子的无电Ni-B电镀液，络合剂 用于镍离子，镍离子还原剂和氨（NH 4+）。 无电镀Ni-B电镀液可以降低所得镀膜的硼含量，而不增加电镀速率，并形成具有FCC晶体结构的Ni-B合金膜。

公开(公告)号：US06462969B1

公开(公告)日：2002-10-08

申请号：US09984273

申请日：2001-10-29

申请人： Osamu Sato ,  Hiroaki Inoue

发明人： Osamu Sato ,  Hiroaki Inoue

IPC分类号： H02H908

CPC分类号： H02M7/23 ,  H02M3/1584

摘要： In a power supply system connected to a load, a plurality of DC power source units are connected in parallel. Each DC power source unit is provided with a unit rated current value Iu, and outputs a unit current in accordance with a target value. A required load capacity provider provides a capacity value Is required in the load. An operating condition detector detects the number m of DC power supply unit which is in an operating condition among the DC power source units. A target value calculator calculates a value obtained by dividing the value Is with the value m, and provides the calculated value Is/m to the respective operating DC power supply unit as the target value.

摘要翻译： 在连接到负载的电源系统中，多个DC电源单元并联连接。 每个DC电源单元具有单位额定电流值Iu，并且根据目标值输出单位电流。 所需的负载能力提供商提供负载所需的容量值。 操作状态检测器检测直流电源单元中处于工作状态的直流电源单元的数量m。 目标值计算器计算通过将值Is除以值m获得的值，并将计算值Is / m提供给相应的操作DC电源单元作为目标值。