利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

316 条记录 (耗时 0.028 秒)

    SRAM with Improved Program and Sensing Margin for Scaled Nanosheet Devices
    112.
    发明公开
    SRAM with Improved Program and Sensing Margin for Scaled Nanosheet Devices 审中-公开

    公开(公告)号：US20240098961A1

    公开(公告)日：2024-03-21

    申请号：US17949579

    申请日：2022-09-21

    申请人： International Business Machines Corporation

    发明人： Min Gyu Sung ,  Ruilong Xie ,  Heng Wu ,  Julien Frougier

    IPC分类号： H01L27/11

    CPC分类号： H01L27/1108

    摘要： An integrated circuit structure includes a memory cell and multiple transistors therein. The multiple transistors are formed using channels including a stack having alternating layers of conductive semiconductor material and layers of other material that are insulative. Two or more of the multiple transistors have a same number of layers of the conductive semiconductor material in corresponding channel regions but have different numbers of active layers and inactive layers of the conductive semiconductor material. An active layer is a layer forming a channel in the channel region that is electrically coupled to S/D regions in a corresponding transistor, while a floating layer is a layer in the channel region electrically isolated from the S/D regions in the corresponding transistor. Methods for forming the integrated circuit structure are disclosed.

    MAGNETORESISTIVE RANDOM ACCESS MEMORY WITH DATA SCRUBBING
    114.
    发明公开
    MAGNETORESISTIVE RANDOM ACCESS MEMORY WITH DATA SCRUBBING 审中-公开

    公开(公告)号：US20240087630A1

    公开(公告)日：2024-03-14

    申请号：US17931464

    申请日：2022-09-12

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Heng Wu ,  Krishna Thangaraj ,  Eric Raymond Evarts

    IPC分类号： G11C11/16

    CPC分类号： G11C11/1677 ,  G11C11/1673 ,  G11C11/1693

    摘要： Embodiments are disclosed for a system that includes a data scrubbing circuit, a magnetoresistive random access memory (MRAM) having a memory array, and an analog persistent vital information circuit (APVIC) that performs a method. The method includes resetting weights corresponding to blocks of the memory array. The method further includes adjusting the weights based on a timer, data accesses on the memory blocks, and weight change values corresponding to the weights. The method also includes determining, in response to the timer, a data scrubbing threshold based on ambient temperature and magnetic field strength. The method additionally includes determining one of the weights meets the data scrubbing threshold. Further, the method includes providing, in response to the determination, an indication that a data scrubber, scrub one of the memory blocks corresponding to the weight that meets the data scrubbing threshold. Also, the method includes resetting the weight.

    HIGH DENSITY MEMORY WITH STACKED NANOSHEET TRANSISTORS
    119.
    发明公开
    HIGH DENSITY MEMORY WITH STACKED NANOSHEET TRANSISTORS 审中-公开

    公开(公告)号：US20230309324A1

    公开(公告)日：2023-09-28

    申请号：US17705320

    申请日：2022-03-26

    申请人： International Business Machines Corporation

    发明人： Heng Wu ,  Tenko Yamashita ,  Sanjay C. Mehta ,  Junli Wang

    IPC分类号： H01L27/24

    CPC分类号： H01L27/2436

    摘要： A high density memory apparatus includes a plurality of transistors vertically stacked on top of each other. The plurality of transistors share a common source structure, but each of the plurality of transistors has its own horizontal nanosheet and gate stack that are separate from respective horizontal channel structures and gate stacks of the others of the plurality of transistors. Ends of the nanosheets distal from the gate stacks are doped to act as drains for the transistors. Each of a plurality of two-terminal memory units is electrically connected to the drain end of a corresponding one of the nanosheets. Some embodiments achieve in excess of 5000 memory bits/square micrometer (μm2); in some embodiments, in excess of 6000 bits/μm2.