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    REDUNDANT DATA LOG RETRIEVAL IN MULTI-PROCESSOR DEVICE
    112.
    发明公开
    REDUNDANT DATA LOG RETRIEVAL IN MULTI-PROCESSOR DEVICE 审中-公开

    公开(公告)号：US20230161599A1

    公开(公告)日：2023-05-25

    申请号：US17968488

    申请日：2022-10-18

    Applicant: Rambus Inc.

    Inventor： Evan Lawrence Erickson

    IPC: G06F9/4401 ,  H04L67/141

    CPC classification number: G06F9/4406 ,  H04L67/141

    Abstract: A device includes interface circuitry to receive requests from at least one host system, a primary processor coupled to the interface circuitry, and a secure processor coupled to the primary processor. In response to a failure of the primary processor, the secure processor is to: verify a log retrieval command received via the interface circuitry, wherein the log retrieval command is cryptographically signed; in response to the verification, retrieve crash dump data stored in memory that is accessible by the primary processor; generate a log file that comprises the retrieved crash dump data; and cause the log file to be transmitted to the at least one host system over a sideband link that is coupled externally to the interface circuitry.

    Cache Memory That Supports Tagless Addressing
    113.
    发明公开
    Cache Memory That Supports Tagless Addressing 审中-公开

    公开(公告)号：US20230153251A1

    公开(公告)日：2023-05-18

    申请号：US17992443

    申请日：2022-11-22

    Applicant: Rambus Inc.

    Inventor： Hongzhong Zheng ,  Trung A. Diep

    IPC: G06F12/1045 ,  G06F12/0802 ,  G06F12/1009

    CPC classification number: G06F12/1063 ,  G06F12/0802 ,  G06F12/1009 ,  G06F12/1054

    Abstract: The disclosed embodiments relate to a computer system with a cache memory that supports tagless addressing. During operation, the system receives a request to perform a memory access, wherein the request includes a virtual address. In response to the request, the system performs an address-translation operation, which translates the virtual address into both a physical address and a cache address. Next, the system uses the physical address to access one or more levels of physically addressed cache memory, wherein accessing a given level of physically addressed cache memory involves performing a tag-checking operation based on the physical address. If the access to the one or more levels of physically addressed cache memory fails to hit on a cache line for the memory access, the system uses the cache address to directly index a cache memory, wherein directly indexing the cache memory does not involve performing a tag-checking operation and eliminates the tag storage overhead.

    MANAGING MEMORY MAINTENANCE OPERATIONS IN A MEMORY SYSTEM HAVING BACKING STORAGE MEDIA
    117.
    发明申请
    MANAGING MEMORY MAINTENANCE OPERATIONS IN A MEMORY SYSTEM HAVING BACKING STORAGE MEDIA 有权

    公开(公告)号：US20230135017A1

    公开(公告)日：2023-05-04

    申请号：US18074217

    申请日：2022-12-02

    Applicant: Rambus Inc.

    Inventor： Collins Williams ,  Michael Miller ,  Kenneth Wright

    IPC: G06F12/0815 ,  G11C14/00

    Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory system is disclosed. The memory system includes volatile memory configured as a cache. The cache stores first data at first storage locations. Backing storage media couples to the cache. The backing storage media stores second data in second storage locations corresponding to the first data. Logic uses a presence or status of first data in the first storage locations to cease maintenance operations to the stored second data in the second storage locations.

    FLASH MEMORY DEVICE HAVING A CALIBRATION MODE
    119.
    发明申请
    FLASH MEMORY DEVICE HAVING A CALIBRATION MODE 有权

    公开(公告)号：US20230119579A1

    公开(公告)日：2023-04-20

    申请号：US18082446

    申请日：2022-12-15

    Applicant: Rambus Inc.

    Inventor： Pravin Kumar Venkatesan ,  Liji Gopalakrishnan ,  Kashinath Ullhas Prabhu ,  Makarand Ajit Shirasgaonkar

    IPC: G06F13/16

    Abstract: A method of operation of a flash integrated circuit (IC) memory device is described. The flash IC memory device has an array of memory cells and an interface to receive control, address and data signals using an internal reference voltage. The method includes, at boot-up, initializing the internal reference voltage to a default voltage. At boot-up, the interface is operable to receive, using the internal reference voltage, signals having a first voltage swing at a first signaling frequency. The method includes receiving a first command that specifies calibration of the interface during a calibration mode. The calibration mode is used to calibrate the interface to operate at a second signaling frequency and receive signals having a second voltage swing. The second voltage swing is smaller than the first voltage swing and the second signaling frequency is higher than the first signaling frequency.

    High capacity, high performance memory system
    120.
    发明授权
    High capacity, high performance memory system 有权

    公开(公告)号：US11630607B2

    公开(公告)日：2023-04-18

    申请号：US17521399

    申请日：2021-11-08

    Applicant: Rambus Inc.

    Inventor： Frederick Ware

    IPC: G06F3/06 ,  G06F12/06 ,  G06F13/40 ,  G06F13/16 ,  G06F13/42

    Abstract: Memory devices and a memory controller that controls such memory devices. Multiple memory devices receive commands and addresses on a command/address (C/A) bus that is relayed point-to-point by each memory device. Data is received and sent from these devices to/from a memory controller in a point-to-point configuration by adjusting the width of each individual data bus coupled between the individual memory devices and the memory controller. Along with the C/A bus are clock signals that are regenerated by each memory device and relayed. The memory controller and memory devices may be packaged on a single substrate using package-on-package technology. Using package-on-package technology allows the relayed C/A signals to connect from memory device to memory device using wire bonding. Wirebond connections provide a short, high-performance signaling environment for the chip-to-chip relaying of the C/A signals and clocks from one memory device to the next in the daisy-chain.

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