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公开(公告)号：US09407283B2
公开(公告)日：2016-08-02
申请号：US14055980
申请日：2013-10-17
Applicant: ANALOG DEVICES TECHNOLOGY
Inventor： Trevor Clifford Caldwell , Richard E. Schreier
Abstract: A delta-sigma modulator is configured to sense and convert an electromagnetic field into a digital signal. An exemplary delta-sigma modulator includes a sensor component, such as an LC resonator, that is configured to sense the electromagnetic field and generate an input analog signal, where the delta-sigma modulator is configured to convert the input analog signal to the digital signal. Delta-sigma modulator can include an analog-to-digital converter coupled to the sensor component that receives and converts the input analog signal to the digital signal. Delta-sigma modulator can further include a digital-to-analog converter (DAC) coupled to the resonator and the ADC, the DAC configured to receive the digital signal from the ADC and generate a feedback analog signal.
Abstract translation: Δ-Σ调制器被配置为感测并将电磁场转换成数字信号。 示例性的Δ-Σ调制器包括诸如LC谐振器的传感器组件，其被配置为感测电磁场并产生输入模拟信号，其中Δ-Σ调制器被配置为将输入的模拟信号转换为数字信号 。 Δ-Σ调制器可以包括耦合到传感器组件的模数转换器，其接收并将输入的模拟信号转换成数字信号。 Δ-Σ调制器还可以包括耦合到谐振器和ADC的数模转换器（DAC），DAC被配置为从ADC接收数字信号并产生反馈模拟信号。
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公开(公告)号：US20160164506A1
公开(公告)日：2016-06-09
申请号：US14563559
申请日：2014-12-08
Applicant: Analog Devices Technology
Inventor： Sherwin Paul Almazon , George Redfield Spalding, JR.
IPC: H03K4/02 , H03K5/1534 , H03K17/687
CPC classification number: H03K5/1534 , H03K3/0231 , H03K5/153 , H03K17/6871
Abstract: A timer circuit is provided comprising: a resistor; a programmable gain circuit coupled to amplify the reference level based upon a resistor and a selected gain; a detection circuit coupled to identify the amplified reference level based upon a resistor; a selection circuit configured to select the gain based at least in part upon the identified amplified reference level based upon a resistor; a comparator circuit configured to transition between providing a signal having a first value and providing a signal having a second value based at least in part upon comparisons of a reactive circuit element excitation level with the amplified reference level based upon a resistor and with a second reference level; and reactive circuit element excitation circuit configured to reverse excitation of the reactive circuit element in response to the comparator circuit transitioning between providing the signal having the first value and providing the signal having the second value.
Abstract translation: 提供了一种定时器电路，包括：电阻器; 可编程增益电路，其耦合以基于电阻器和选定的增益放大参考电平; 检测电路，其被耦合以基于电阻器来识别放大的参考电平; 选择电路，被配置为至少部分地基于基于电阻器的所识别的放大参考电平来选择增益; 比较器电路，被配置为在提供具有第一值的信号之间转换并且至少部分地基于电抗器电路元件激励电平与基于电阻器的放大参考电平进行比较并提供具有第二值的信号，并且具有第二参考 水平; 以及无功电路元件激励电路，其被配置为响应于在提供具有第一值的信号和提供具有第二值的信号之间的比较器电路转换来反向无功电路元件的激励。
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公开(公告)号：US09312840B2
公开(公告)日：2016-04-12
申请号：US14194107
申请日：2014-02-28
Applicant: ANALOG DEVICES TECHNOLOGY
Inventor： Yunzhi Dong , Zhao Li , Richard E. Schreier , Hajime Shibata , Trevor Clifford Caldwell
CPC classification number: H03K5/159 , H03M1/0626 , H03M1/14 , H03M1/145 , H03M1/38 , H03M3/414 , H03M3/464
Abstract: This disclosure describes techniques and methodologies of using passive continuous time (CT) delay line for high-speed CT analog-to-digital converter (ADC) applications. In a continuous-time residual producing stage common to these CT ADCs, a proper delay between the analog input and DAC output is crucial. Specifically, using an inductor-capacitor (LC) lattice based delay element to enable high-performance CT pipeline ADC and CT delta-sigma (ΔΣ) ADC. The use of an LC lattice based delay element provides wide-band group delay for continuous-time signals with well-controlled impedance. This will be an essential circuit component to build a high-performance CT ADCs especially in architectures where the generation of a low-noise and low-distortion residual between the CT signal and its digitized version is needed. LC lattice based delay element enables noise-free, distortion-free wideband delay that is required for high speed continuous-time pipeline ADC and delta-sigma ADC.
Abstract translation: 本公开描述了使用被动连续时间（CT）延迟线用于高速CT模数转换器（ADC）应用的技术和方法。 在这些CT ADC通用的连续时间残留产生阶段，模拟输入和DAC输出之间的适当延迟至关重要。 具体来说，使用电感 - 电容（LC）晶格延迟元件来实现高性能CT流水线ADC和CT delta-sigma（＆Dgr＆amp; Sgr）ADC。 使用基于LC晶格的延迟元件为具有良好控制的阻抗的连续时间信号提供宽带群延迟。 这将是构建高性能CT ADC的重要电路元件，特别是在需要CT信号与其数字化版本之间产生低噪声和低失真残差的架构中。 基于LC晶格的延迟元件实现了高速连续时间流水线ADC和Δ-ΣADC所需的无噪声，无失真的宽带延迟。
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124.发明申请WIRELESS CHARGING PLATFORM USING ENVIRONMENT BASED BEAMFORMING FOR WIRELESS SENSOR NETWORK 审中-公开使用无线传感器网络的基于环境的波束形成无线充电平台公开(公告)号：US20160049824A1
公开(公告)日：2016-02-18
申请号：US14461003
申请日：2014-08-15
Applicant: ANALOG DEVICES TECHNOLOGY
Inventor： Yosef Stein , Roman Trogan , Haim Primo
CPC classification number: H02J7/025 , H02J50/20 , H02J50/23 , H02J50/90 , H04B5/0037 , H04B7/0617 , H04W4/70 , H04W16/28 , H04W52/04 , H04W64/00 , H04W84/18 , H04W88/16
Abstract: A wireless charging network system is disclosed that includes wirelessly charged sensor nodes. The wireless network system can include a gateway node configured to aggregate data from sensor nodes within a coverage area of the gateway node. The gateway node is further configured to wirelessly transmit power to the sensor nodes using a beamformed signal, wherein the gateway node adjusts the beamformed signal to maximize wireless power transfer to sensor nodes within each sector of the coverage area. Location information can be used to adjust the beamformed signal. For example, in various embodiments, the gateway node includes a beamformer sector profile table that defines channel adaptive beam profiles for the beamformed signal for each sector of the coverage area. The gateway node can use location information to define the beam profiles.
Abstract translation: 公开了一种包括无线充电传感器节点的无线充电网络系统。 无线网络系统可以包括被配置为从网关节点的覆盖区域内的传感器节点聚合数据的网关节点。 网关节点还被配置为使用波束形成的信号将功率无线传输到传感器节点，其中网关节点调整波束形成的信号以最大化对覆盖区域的每个扇区内的传感器节点的无线功率传输。 位置信息可用于调整波束形成信号。 例如，在各种实施例中，网关节点包括波束形成器扇区轮廓表，其为覆盖区域的每个扇区定义用于波束形成信号的信道自适应波束分布。 网关节点可以使用位置信息来定义波束轮廓。
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125.发明授权Analog to digital converter and a method of operating an analog to digital converter 有权模数转换器和一种操作模数转换器的方法公开(公告)号：US09191023B2
公开(公告)日：2015-11-17
申请号：US14173407
申请日：2014-02-05
Applicant: ANALOG DEVICES TECHNOLOGY
Inventor： Christopher Peter Hurrell
CPC classification number: H03M1/442 , H03G3/3052 , H03M1/00 , H03M1/002 , H03M1/0678 , H03M1/12 , H03M1/1295 , H03M1/468 , H03M1/804
Abstract: Example embodiments of this disclosure can provide an apparatus, a system, and a method of correcting for charge lost from a sampling capacitor as a result of an analog to digital conversion being performed. In an embodiment, there is provided a method of operating an analog to digital converter comprising at least a first sampling capacitor used to sample an input signal, where the method can further comprise a correction step of modifying the voltage across the at least first sampling capacitor, the correction step being performed prior to commencing an acquire phase.
Abstract translation: 本公开的示例性实施例可以提供一种装置，系统和校正由于执行模数转换而从采样电容器损失的电荷的方法。 在一个实施例中，提供了一种操作模数转换器的方法，该方法至少包括用于对输入信号进行采样的第一采样电容器，其中该方法还可以包括校正步骤，该校正步骤修改至少第一采样电容器 ，所述校正步骤在开始获取阶段之前执行。
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Patent Agency Ranking
公开(公告)号：US20150303887A1
公开(公告)日：2015-10-22
申请号：US14258634
申请日：2014-04-22
Applicant: Analog Devices Technology
Inventor： EBERHARD BRUNNER , JEFF VENUTI
CPC classification number: H03G3/3042 , H03F3/19 , H03F3/4508 , H03F2200/336 , H03F2200/451 , H03F2203/45116 , H03F2203/45154 , H03F2203/45306 , H03G1/0023
Abstract: A system has a baseband gain stage to receive incoming in-phase and quadrature voltage signals and output in-phase and quadrature current signals, a mixer core arranged to receive the in-phase and quadrature current signals and output radio frequency signals, and a variable gain amplifier to receive the radio frequency signals and produce a broadband radio signal.
Abstract translation: 系统具有基带增益级，用于接收输入的同相和正交电压信号并输出同相和正交电流信号，混频器核被布置成接收同相和正交电流信号并输出射频信号，以及变量 增益放大器接收射频信号并产生宽带无线电信号。
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公开(公告)号：US20150249445A1
公开(公告)日：2015-09-03
申请号：US14194107
申请日：2014-02-28
Applicant: ANALOG DEVICES TECHNOLOGY
Inventor： Yunzhi Dong , Zhao Li , Richard E. Schreier , Hajime Shibata , Trevor Clifford Caldwell
CPC classification number: H03K5/159 , H03M1/0626 , H03M1/14 , H03M1/145 , H03M1/38 , H03M3/414 , H03M3/464
Abstract: This disclosure describes techniques and methodologies of using passive continuous time (CT) delay line for high-speed CT analog-to-digital converter (ADC) applications. In a continuous-time residual producing stage common to these CT ADCs, a proper delay between the analog input and DAC output is crucial. Specifically, using an inductor-capacitor (LC) lattice based delay element to enable high-performance CT pipeline ADC and CT delta-sigma (ΔΣ) ADC. The use of an LC lattice based delay element provides wide-band group delay for continuous-time signals with well-controlled impedance. This will be an essential circuit component to build a high-performance CT ADCs especially in architectures where the generation of a low-noise and low-distortion residual between the CT signal and its digitized version is needed. LC lattice based delay element enables noise-free, distortion-free wideband delay that is required for high speed continuous-time pipeline ADC and delta-sigma ADC.
Abstract translation: 本公开描述了使用被动连续时间（CT）延迟线用于高速CT模数转换器（ADC）应用的技术和方法。 在这些CT ADC通用的连续时间残留产生阶段，模拟输入和DAC输出之间的适当延迟至关重要。 具体来说，使用电感 - 电容（LC）晶格延迟元件来实现高性能CT流水线ADC和CT delta-sigma（＆Dgr＆amp; Sgr）ADC。 使用基于LC晶格的延迟元件为具有良好控制的阻抗的连续时间信号提供宽带群延迟。 这将是构建高性能CT ADC的重要电路元件，特别是在需要CT信号与其数字化版本之间产生低噪声和低失真残差的架构中。 基于LC晶格的延迟元件实现了高速连续时间流水线ADC和Δ-ΣADC所需的无噪声，无失真的宽带延迟。
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公开(公告)号：US20150211915A1
公开(公告)日：2015-07-30
申请号：US14165971
申请日：2014-01-28
Applicant: ANALOG DEVICES TECHNOLOGY
Inventor： James E. Scarlett , Thomas G. O'Dwyer , Christopher W. Hyde
IPC: G01F23/26
CPC classification number: G01F23/263 , G01F23/266 , G01F23/268 , G01N35/1011 , G01N2035/1025
Abstract: Various methods and systems are provided to control a probe moving towards fluid held in a container. The probe is moved towards the fluid to take a sample of the fluid in the container. To take a sample, probe is actuated to hit the fluid surface and to pass the fluid surface by a predetermined distance. Capacitive sensing which incorporates the probe itself is used to support an approach engine for controlling the motion of the probe. The approach engine determines the speed of the probe based on capacitance measurements, and in some cases based on position information of the probe. The approach engine ensures the probe hits the surface of the fluid in the container in order to take a sample while ensuring the probe does not hit the bottom of the container.
Abstract translation: 提供了各种方法和系统来控制朝向容纳在容器中的流体移动的探头。 探针朝向流体移动，以将容器中的流体样本取样。 为了取样，启动探针以撞击流体表面并使流体表面通过预定距离。 采用探头本身的电容感测用于支持用于控制探头运动的进场引擎。 方法引擎基于电容测量来确定探针的速度，并且在某些情况下基于探针的位置信息来确定探针的速度。 进近引擎确保探针撞击容器中流体的表面，以便在确保探头未碰到容器底部的同时取样。
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公开(公告)号：US09065337B2
公开(公告)日：2015-06-23
申请号：US13775820
申请日：2013-02-25
Applicant: Analog Devices Technology
Inventor： Hirohisa Tanabe , Kenji Tomiyoshi
CPC classification number: H02M3/1582 , H02M3/156 , H02M2001/0009
Abstract: An inductor current emulation circuit for use with a switching converter in which regulating the output voltage includes comparing an output which varies with the difference between the output voltage and a reference voltage with a ‘ramp’ signal which emulates the current in the output inductor. A current sensing circuit produces an output which varies with the current in the switching element that is turned on during the ‘off’ time, an emulated current generator circuit produces the ‘ramp’ signal during both ‘off’ and ‘on’ times, a comparator circuit compares the ‘ramp’ signal with at least one threshold voltage which varies with the sensed current and toggles an output when the ‘ramp’ exceeds the thresholds, and a feedback circuit produces an output which adjusts the ‘ramp’ signal each time the comparator circuit output toggles until the ‘ramp’ signal no longer exceeds the threshold voltages.
Abstract translation: 一种与开关转换器一起使用的电感器电流仿真电路，其中调节输出电压包括将输出与输出电压和参考电压之间的差值进行比较，其中的“斜坡”信号模拟输出电感器中的电流。 电流感测电路产生随着在“关断”时间期间导通的开关元件中的电流而变化的输出，仿真电流发生器电路在“断开”和“打开”时间期间产生“斜坡”信号，a 比较器电路将“斜坡”信号与至少一个随感测电流变化的阈值电压进行比较，并在“斜坡”超过阈值时切换输出，反馈电路产生一个输出，每次输出调整“斜坡”信号 比较器电路输出切换直到“斜坡”信号不再超过阈值电压。
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公开(公告)号：US09048847B2
公开(公告)日：2015-06-02
申请号：US14034917
申请日：2013-09-24
Applicant: Analog Devices Technology
Inventor： David J McLaurin , Christopher W Angell , Michael F Keaveney
CPC classification number: H03L7/1976 , H03L7/085 , H03L7/104 , H03L7/199 , H03L7/23
Abstract: Apparatus and methods for synchronizing phase-locked loops (PLLs) are provided. In certain implementations, a fractional-N synthesizer includes a PLL and a control circuit that controls a division value of the PLL. The control circuit includes an interpolator, a reset phase adjustment calculator, and a synchronization circuit. The interpolator can control a fractional portion of the PLL's division value. The reset phase adjustment calculator can include a counter for counting a number of cycles of the reference clock signal since initialization of the fractional-N synthesizer, and the reset phase adjustment calculator can generate a phase adjustment signal based on the count. The synchronization circuit can synchronize the PLL in response to a synchronization signal, and can correct for a synchronization phase error indicated by the phase adjustment signal.
Abstract translation: 提供了用于同步锁相环（PLL）的装置和方法。 在某些实现中，分数N合成器包括PLL和控制PLL的分频值的控制电路。 控制电路包括内插器，复位相位调整计算器和同步电路。 内插器可以控制PLL分频值的小数部分。 复位相位调整计算器可以包括一个计数器，用于对分数N合成器的初始化后的参考时钟信号的周期数进行计数，并且复位相位调整计算器可以基于计数产生相位调整信号。 同步电路可以响应于同步信号来同步PLL，并且可以校正由相位调整信号指示的同步相位误差。
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