公开(公告)号：US20190296145A1

公开(公告)日：2019-09-26

申请号：US16316337

申请日：2016-09-26

Applicant: Intel Corporation

Inventor： Cheng-Ying HUANG ,  Willy RACHMADY ,  Matthew V. METZ ,  Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Sean T. MA ,  Harold KENNEL

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/66 ,  H01L29/417 ,  H01L29/20

Abstract: A buffer layer is deposited on a substrate. A first III-V semiconductor layer is deposited on the buffer layer. A second III-V semiconductor layer is deposited on the first III-V semiconductor layer. The second III-V semiconductor layer comprises a channel portion and a source/drain portion. The first III-V semiconductor layer acts as an etch stop layer to etch a portion of the second III-V semiconductor layer to form the source/drain portion.

公开(公告)号：US20190252020A1

公开(公告)日：2019-08-15

申请号：US16320023

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Rafael RIOS ,  Abhishek Anil SHARMA ,  Van H. LE ,  Gilbert William DEWEY ,  Jack T. KAVALIEROS

IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: G11C13/0007 ,  G11C8/16 ,  G11C13/003 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/15 ,  G11C2213/56 ,  G11C2213/74 ,  G11C2213/79 ,  G11C2213/82 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/1666

Abstract: A two transistor, one resistor gain cell and a suitable storage element are described. In some embodiments the gain cell has a resistive memory element coupled to a common node at one end to store a value and to a source line at another end, the value being read as conductivity between the common node and the source line of the resistive memory element, a write transistor having a source coupled to a bit line, a gate coupled to a write line, and a drain coupled to the common node to write a value at the bit line to the resistive memory element upon setting the write line high, and a read transistor having a source coupled to a bit line read line and a gate coupled to the common node to read the value written to the resistive memory element as a value at the second transistor gate.

公开(公告)号：US20190172921A1

公开(公告)日：2019-06-06

申请号：US16325333

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Gilbert DEWEY ,  Van H. LE ,  Rafael RIOS ,  Jack T. KAVALIEROS ,  Shriram SHIVARAMAN

IPC: H01L29/45 ,  H01L29/786 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/443

Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing a high mobility low contact resistance semiconducting oxide in metal contact vias for thin film transistors. For instance, there is disclosed in accordance with one embodiment an oxide semiconductor transistor, having therein: a substrate layer; a channel layer formed atop the substrate; a metal gate and a gate oxide material formed atop the semiconducting oxide material of the channel layer; spacers positioned adjacent to the gate and gate oxide material; a dielectric layer formed atop the channel layer, the dielectric layer encompassing the spacers, the gate, and the gate oxide material; contact vias opened into the dielectric material forming an opening through the dielectric layer to the channel layer; a high mobility liner material lining the contact vias and in direct contact with the channel layer, the high mobility liner formed from a high mobility oxide material; and metallic contact material filling the contact vias opened into the dielectric material and separated from the channel layer by the high mobility liner of the contact vias. Other related embodiments are disclosed.

公开(公告)号：US20190138893A1

公开(公告)日：2019-05-09

申请号：US16147176

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Abhishek SHARMA ,  Jack T. KAVALIEROS ,  Ian A. YOUNG ,  Ram KRISHNAMURTHY ,  Sasikanth MANIPATRUNI ,  Uygar AVCI ,  Gregory K. CHEN ,  Amrita MATHURIYA ,  Raghavan KUMAR ,  Phil KNAG ,  Huseyin Ekin SUMBUL ,  Nazila HARATIPOUR ,  Van H. LE

IPC: G06N3/063 ,  H01L27/108 ,  H01L27/11 ,  H01L27/11502 ,  G06N3/04 ,  G06F17/16

Abstract: An apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The memory array includes an embedded dynamic random access memory (eDRAM) memory array. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes a switched capacitor circuit. The switched capacitor circuit includes a back-end-of-line (BEOL) capacitor coupled to a thin film transistor within the metal/dielectric layers of the semiconductor chip. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes an accumulation circuit. The accumulation circuit includes a ferroelectric BEOL capacitor to store a value to be accumulated with other values stored by other ferroelectric BEOL capacitors.

公开(公告)号：US20190103486A1

公开(公告)日：2019-04-04

申请号：US16099532

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： Willy RACHMADY ,  Van H. LE ,  Matthew V. METZ ,  Benjamin CHU-KUNG ,  Ashish AGRAWAL ,  Jack T. KAVALIEROS

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L23/31 ,  H01L23/29

Abstract: An apparatus including a transistor device including a channel disposed on a substrate between a source and a drain, a gate electrode disposed on the channel, wherein the channel includes a length dimension between source and drain that is greater than a length dimension of the gate electrode such that there is a passivated underlap between an edge of the gate electrode and an edge of the channel relative to each of the source and the drain. A method including forming a channel of a transistor device on a substrate; forming first and second passivation layers on a surface of substrate on opposite sides of the channel; forming a gate stack on the channel between first and second passivation layers; and forming a source on the substrate between the channel and the first passivation layer and a drain on the substrate between the channel and the second passivation layer.

公开(公告)号：US20180323264A1

公开(公告)日：2018-11-08

申请号：US15773549

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Van H. LE ,  Rafael RIOS ,  Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Marko RADOSAVLJEVIC

IPC: H01L29/24 ,  H01L29/78 ,  H01L29/417 ,  H01L29/45 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L21/768 ,  H01L21/443 ,  H01L29/04

CPC classification number: H01L29/24 ,  H01L21/02565 ,  H01L21/02592 ,  H01L21/443 ,  H01L21/76802 ,  H01L21/76877 ,  H01L27/12 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/41758 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785

Abstract: Embodiments of the invention include non-planar InGaZnO (IGZO) transistors and methods of forming such devices. In an embodiment, the IGZO transistor may include a substrate and an IGZO fin formed above the substrate. Embodiments may include a source contact and a drain contact that are formed adjacent to more than one surface of the IGZO fin. Additionally, embodiments may include a gate electrode formed between the source contact and the drain contact. The gate electrode may be separated from the IGZO layer by a gate dielectric. In one embodiment, the IGZO transistor is a fmfet transistor. In another embodiment the IGZO transistor is a nanowire or a nanoribbon transistor. Embodiments of the invention may also include a non-planar IGZO transistor that is formed in the back end of line stack (BEOL) of an integrated circuit chip.

公开(公告)号：US20180315827A1

公开(公告)日：2018-11-01

申请号：US15770468

申请日：2015-12-17

Applicant: Intel Corporation

Inventor： Sean T. MA ,  Willy RACHMADY ,  Matthew V. METZ ,  Chandra S. MOHAPATRA ,  Gilbert DEWEY ,  Nadia M. RAHHAL-ORABI ,  Jack T. KAVALIEROS ,  Anand S. MURTHY

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/205 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L29/4966 ,  H01L21/28264 ,  H01L29/1054 ,  H01L29/205 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851

Abstract: An apparatus including a non-planar body on a substrate, the body including a channel on a blocking material, and a gate stack on the body, the gate stack including a first gate electrode material including a first work function disposed on the channel material and a second gate electrode material including a second work function different from the first work function disposed on the channel material and on the blocking material. A method including forming a non-planar body on a substrate, the non-planar body including a channel on a blocking material, and forming a gate stack on the body, the gate stack including a first gate electrode material including a first work function disposed on the channel and a second gate electrode material including a second work function different from the first work function disposed on the channel and on the blocking material.

公开(公告)号：US20180261498A1

公开(公告)日：2018-09-13

申请号：US15779442

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Sanaz K. GARDNER ,  Willy RACHMADY ,  Van H. LE ,  Matthew V. METZ ,  Seiyon KIM ,  Ashish AGRAWAL ,  Jack T. KAVALIEROS

IPC: H01L21/768 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762

Abstract: Related fields of the present disclosure are in the field of transistor devices, and in particular, FinFET device structures formed using aspect ratio trapping trench (ART) process techniques. For example, a FinFET device consistent with the present disclosure comprises a first fin structure including a first upper fin portion atop a first lower fin portion and a second fin structure including a second upper fin portion atop a second lower fin portion. The first and second upper fin structures include a Group IV material and the first and second lower fin structures include a Group III-V material.

公开(公告)号：US20180226496A1

公开(公告)日：2018-08-09

申请号：US15771998

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Sanaz K. GARDNER ,  Willy RACHMADY ,  Van H. LE ,  Matthew V. METZ ,  Seiyon KIM ,  Ashish AGRAWAL ,  Jack T. KAVALIEROS

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/092 ,  H01L29/267 ,  H01L29/10 ,  H01L21/02 ,  H01L21/306

CPC classification number: H01L29/66818 ,  B82Y10/00 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02532 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02639 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/30625 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/107 ,  H01L29/1079 ,  H01L29/16 ,  H01L29/20 ,  H01L29/267 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/66522 ,  H01L29/775 ,  H01L29/785 ,  H01L29/7854

Abstract: A transistor having an ultra thin fin profile and its method of fabrication is described. The transistor comprises a semiconductor substrate having an insulation layer formed on a semiconductor substrate. A fin extends from the semiconductor substrate. The fin has a subfin portion on the semiconductor substrate and an active fin portion on the subfin portion. The subfin portion is disposed in a trench formed in the insulation layer. The subfin portion comprises a III-V semiconductor material and the active fin portion comprises a group IV semiconductor material.

公开(公告)号：US20180204947A1

公开(公告)日：2018-07-19

申请号：US15570742

申请日：2015-06-16

Applicant: Intel Corporation

Inventor： Willy RACHMADY ,  Matthew V. METZ ,  Van H. LE ,  Ravi PILLARISETTY ,  Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Ashish AGRAWAL

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/762 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/02639 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785

Abstract: A subfin layer is deposited in a trench in an insulating layer on the substrate. A fin is deposited on the subfin layer. The fin has a top portion and opposing sidewalls. The fin comprises a first semiconductor material. The subfin layer comprises a III-V semiconductor material.