公开(公告)号：US20120190196A1

公开(公告)日：2012-07-26

申请号：US13422445

申请日：2012-03-16

申请人： Mukta G. Farooq ,  Emily R. Kinser ,  Richard Wise ,  Hakeem Yusuff

发明人： Mukta G. Farooq ,  Emily R. Kinser ,  Richard Wise ,  Hakeem Yusuff

IPC分类号： H01L21/768

CPC分类号： H01L21/76847 ,  H01L21/0337 ,  H01L21/32136 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A method includes patterning a photoresist layer on a structure to define an opening and expose a first planar area on a substrate layer, forming doped portions of the substrate layer in the first planar area, removing a portion of the photoresist to form a second opening defining a second planar area on the substrate layer, and etching to form a first cavity having a first depth defined by the first opening to expose a first contact in the structure and to form a second cavity defined by the second opening to expose a second contact in the structure.

摘要翻译： 一种方法包括在结构上图案化光致抗蚀剂层以限定开口并暴露衬底层上的第一平面区域，在第一平面区域中形成衬底层的掺杂部分，去除光致抗蚀剂的一部分以形成限定 在衬底层上的第二平面区域，以及蚀刻形成具有由第一开口限定的第一深度的第一腔体，以暴露结构中的第一接触件，并形成由第二开口限定的第二腔室，以暴露第二接触件 结构。

公开(公告)号：US20120149173A1

公开(公告)日：2012-06-14

申请号：US13398481

申请日：2012-02-16

申请人： Mukta G. Farooq ,  Robert Hannon ,  Subramanian S. Iyer ,  Steven J. Koester ,  Sampath Purushothaman ,  Roy R. Yu

发明人： Mukta G. Farooq ,  Robert Hannon ,  Subramanian S. Iyer ,  Steven J. Koester ,  Sampath Purushothaman ,  Roy R. Yu

IPC分类号： H01L21/30

CPC分类号： H01L27/105 ,  H01L24/11 ,  H01L27/0688 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05024 ,  H01L2224/05147 ,  H01L2224/05184 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05599

摘要： A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer is provided. The first active circuitry layer wafer comprises a P+ portion covered by a P− layer, and the P− layer includes active circuitry. The first active circuitry layer wafer is bonded face down to an interface wafer that includes a first wiring layer, and then the P+ portion of the first active circuitry layer wafer is selectively removed with respect to the P− layer of the first active circuitry layer wafer. Next, a wiring layer is fabricated on the backside of the P− layer. Also provided are a non-transitory computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.

摘要翻译： 提供了一种用于制造3D集成电路结构的方法。 根据该方法，提供第一有源电路层晶片。 第一有源电路层晶片包括由P层覆盖的P +部分，并且P层包括有源电路。 第一有源电路层晶片面向下接合到包括第一布线层的接口晶片，然后相对于第一有源电路层晶片的P层选择性地去除第一有源电路层晶片的P +部分 。 接下来，在P-层的背面上制造布线层。 还提供了编码有用于制造3D集成电路结构的程序的非暂时计算机可读介质，以及3D集成电路结构。

公开(公告)号：US20120091593A1

公开(公告)日：2012-04-19

申请号：US12904348

申请日：2010-10-14

申请人： Kangguo Cheng ,  Mukta G. Farooq ,  Louis L. Hsu

发明人： Kangguo Cheng ,  Mukta G. Farooq ,  Louis L. Hsu

IPC分类号： H01L23/538 ,  G06F17/50 ,  H01L21/768

CPC分类号： H01L27/0207 ,  G06F17/5081 ,  H01L21/743 ,  H01L21/76898

摘要： A through silicon via (TSV) and a deep trench capacitor (DTCap) or a deep trench isolation (DTI) are simultaneously formed on the same substrate by a single mask and a single reactive ion etching (RIE). The TSV trench is wider and deeper that the DTCap or DTI trench. The TSV and DTCap or DTI are formed with different dielectric materials on the trench sidewalls. The TSV and DTCap or DTI are perfectly aligned.

摘要翻译： 通过单个掩模和单个反应离子蚀刻（RIE）同时在同一衬底上形成贯通硅通孔（TSV）和深沟槽电容器（DTCap）或深沟槽隔离（DTI）。 TSV沟槽比DTCap或DTI沟槽更宽更深。 TSV和DTCap或DTI在沟槽侧壁上形成有不同的介电材料。 TSV和DTCap或DTI完全对齐。

公开(公告)号：US08120175B2

公开(公告)日：2012-02-21

申请号：US11947832

申请日：2007-11-30

申请人： Mukta G. Farooq ,  Ian D. Melville ,  Kevin S. Petrarca

发明人： Mukta G. Farooq ,  Ian D. Melville ,  Kevin S. Petrarca

IPC分类号： H01L23/48

CPC分类号： H01L24/16 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05568 ,  H01L2224/10126 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2224/05541 ,  H01L2224/05005

摘要： A method creates a structure that comprises a carrier connected to an integrated circuit chip by pillars and openings. Thus, in this structure, at least one conductive pillar extends a distance or height from the surface of the integrated circuit chip and a barrier surrounds the lower portion of the conductive pillar such that the barrier covers at least some portion of the height of the pillar that is closest to the chip surface. There is at least one opening in the carrier that is large enough to accommodate the conductive pillar and the barrier, and the conductive pillar and the barrier are positioned in opening. A solder is used in the bottom of the opening to connect the conductive pillar to the bottom of the opening. The barrier prevents the solder from contacting the portion of the conductive pillar protected by the barrier.

摘要翻译： 一种方法产生一种结构，其包括通过柱和开口连接到集成电路芯片的载体。 因此，在这种结构中，至少一个导电柱与集成电路芯片的表面延伸一段距离或高度，并且阻挡层围绕导电柱的下部，使得阻挡层覆盖柱的高度的至少一部分 最接近芯片表面。 载体中至少有一个开口足够大以容纳导电柱和屏障，并且导电柱和屏障位于开口中。 在开口的底部使用焊料将导电柱连接到开口的底部。 屏障防止焊料接触由屏障保护的导电柱的部分。

公开(公告)号：US08076756B2

公开(公告)日：2011-12-13

申请号：US13031195

申请日：2011-02-19

申请人： Michael W. Lane ,  Xiao Hu Liu ,  Thomas M. Shaw ,  Mukta G. Farooq ,  Robert Hannon ,  Ian D. W. Melville

发明人： Michael W. Lane ,  Xiao Hu Liu ,  Thomas M. Shaw ,  Mukta G. Farooq ,  Robert Hannon ,  Ian D. W. Melville

IPC分类号： H01L23/544

CPC分类号： H01L29/0657 ,  H01L21/563 ,  H01L21/78 ,  H01L23/5329 ,  H01L23/562 ,  H01L23/585 ,  H01L24/90 ,  H01L2224/73203 ,  H01L2224/90 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/18301 ,  H01L2924/00

摘要： A semiconductor product comprises a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip. The semiconductor substrate has a top surface and a perimeter. A barrier is formed in the chip within the perimeter. An Ultra Deep Isolation Trench (UDIT) is cut in the top surface of the chip extending down therein between the perimeter and the barrier. A ILD structure with low-k pSICOH dielectric and hard mask layers is formed over the substrate prior to forming the barrier and the UDIT. The ILD structure interconnection structures can be recessed down to the substrate aside from the UDIT.

摘要翻译： 半导体产品包括具有顶表面和包括半导体芯片的底表面的半导体衬底。 半导体衬底具有顶表面和周边。 在周边的芯片中形成屏障。 在深度隔离沟槽（UDIT）中切割在芯片的上表面，其在周边和屏障之间向下延伸。 在形成屏障和UDIT之前，在衬底上形成具有低k pSICOH电介质和硬掩模层的ILD结构。 除了UDIT之外，ILD结构互连结构可以向下凹入底层。

公开(公告)号：US20110281432A1

公开(公告)日：2011-11-17

申请号：US13192120

申请日：2011-07-27

申请人： Mukta G. Farooq ,  Emily R. Kinser

发明人： Mukta G. Farooq ,  Emily R. Kinser

IPC分类号： H01L21/768

CPC分类号： H01L21/76831 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76829 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05572 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05666 ,  H01L2224/11 ,  H01L2224/13006 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2924/00014

摘要： A line trough and a via cavity are formed within a dielectric layer comprising a fluorosilicate glass (FSG) layer. A fluorine depleted adhesion layer is formed within the line trough and the via cavity either by a plasma treatment that removes fluorine from exposed surfaces of the FSG layer, or by deposition of a substantially fluorine-free dielectric layer. Metal is deposited within the line trough and the via cavity to form a metal line and a metal via. The fluorine depleted adhesion layer provides enhanced adhesion to the metal line compared with prior art structures in which a metal line directly contacts a FSG layer. The enhanced adhesion of metal with an underlying dielectric layer provides higher resistance to delamination for a semiconductor package employing lead-free C4 balls on a metal interconnect structure.

摘要翻译： 在包含氟硅酸盐玻璃（FSG）层的电介质层内形成线槽和通孔。 通过从FSG层的暴露表面除去氟的等离子体处理或通过沉积基本上无氟的介电层，在管线槽和通孔内形成氟贫化粘合层。 金属沉积在管线槽和通孔腔内以形成金属线和金属通孔。 与其中金属线直接接触FSG层的现有技术结构相比，氟贫化粘合层提供对金属线的增强的粘合性。 金属与底层电介质层的增强的粘附性对于在金属互连结构上使用无铅C4球的半导体封装提供更高的剥离性。

公开(公告)号：US08017997B2

公开(公告)日：2011-09-13

申请号：US12344697

申请日：2008-12-29

申请人： Ramachandra Divakaruni ,  Mukta G. Farooq ,  Jeffrey P. Gambino ,  Kevin S. Petrarca

发明人： Ramachandra Divakaruni ,  Mukta G. Farooq ,  Jeffrey P. Gambino ,  Kevin S. Petrarca

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L28/60 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/0629 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure including a vertical metal-insulator-metal capacitor, and a method for fabricating the semiconductor structure including the vertical metal-insulator-metal capacitor, each use structural components from a dummy metal oxide semiconductor field effect transistor located and formed over an isolation region located over a semiconductor substrate. The dummy metal oxide field effect transistor may be formed simultaneously with a metal oxide semiconductor field effect transistor located over a semiconductor substrate that includes the isolation region. The metal-insulator-metal capacitor uses a gate as a capacitor plate, a uniform thickness gate spacer as a gate dielectric and a contact via as another capacitor plate. The uniform thickness gate spacer may include a conductor layer for enhanced capacitance. A mirrored metal-insulator-metal capacitor structure that uses a single contact via may also be used for enhanced capacitance.

摘要翻译： 包括垂直金属 - 绝缘体 - 金属电容器的半导体结构以及包括垂直金属 - 绝缘体 - 金属电容器的半导体结构的制造方法，每个都使用位于隔离层上并形成的虚设金属氧化物半导体场效应晶体管的结构部件 区域位于半导体衬底上。 虚拟金属氧化物场效应晶体管可以与位于包括隔离区域的半导体衬底之上的金属氧化物半导体场效应晶体管同时形成。 金属 - 绝缘体 - 金属电容器使用栅极作为电容器板，均匀厚度的栅极间隔物作为栅极电介质和作为另一个电容器板的接触通孔。 均匀厚度的栅极间隔物可以包括用于增强电容的导体层。 使用单个接触通孔的镜像金属 - 绝缘体 - 金属电容器结构也可用于增强电容。

公开(公告)号：US20110175215A1

公开(公告)日：2011-07-21

申请号：US12689455

申请日：2010-01-19

申请人： Mukta G. Farooq ,  Kangguo Cheng ,  Louis Lu-Chen Hsu

发明人： Mukta G. Farooq ,  Kangguo Cheng ,  Louis Lu-Chen Hsu

IPC分类号： H01L23/52 ,  H01L21/77

CPC分类号： H01L23/481 ,  H01L24/05 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/05552

摘要： A method of forming a three-dimensional (3D) chip is provided in which a second chip is present embedded within a first chip. In one embodiment, the method includes forming a first chip including first electrical devices and forming a recess extending from a surface of the first chip. A second chip is formed having second electrical devices. The second chip is then encapsulated within the recess of the first chip. Interconnects are then formed through the first chip into electrical communication with at least one of the second devices on the second chip. A three-dimensional (3D) chip is also provided in which a second chip is embedded within a first chip.

摘要翻译： 提供一种形成三维（3D）芯片的方法，其中第二芯片存在于第一芯片内。 在一个实施例中，该方法包括形成包括第一电气装置并形成从第一芯片的表面延伸的凹部的第一芯片。 形成有第二电气装置的第二芯片。 然后将第二芯片封装在第一芯片的凹槽内。 然后，互连件通过第一芯片形成为与第二芯片上的至少一个第二器件电连通。 还提供了一种三维（3D）芯片，其中第二芯片被嵌入在第一芯片内。

公开(公告)号：US20110171582A1

公开(公告)日：2011-07-14

申请号：US12687289

申请日：2010-01-14

申请人： Mukta G. Farooq ,  Ramona Kei ,  Emily R. Kinser ,  Anthony D. Lisi ,  Richard Wise ,  Hakeem Yusuff

发明人： Mukta G. Farooq ,  Ramona Kei ,  Emily R. Kinser ,  Anthony D. Lisi ,  Richard Wise ,  Hakeem Yusuff

IPC分类号： G03F7/20

CPC分类号： H01L21/76898 ,  H01L21/3085 ,  H01L25/0657 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is disclosed which includes patterning a photoresist layer on a substrate of a structure, removing a first portion of the photoresist layer to expose a first area of the substrate, etching the first area to form a cavity having a first depth, removing a second portion of the photoresist to expose an additional area of the substrate, and etching the cavity to expose a first conductor in the structure and the additional area to expose a second conductor in the structure.

摘要翻译： 公开了一种方法，其包括在结构的衬底上图案化光致抗蚀剂层，去除光致抗蚀剂层的第一部分以暴露衬底的第一区域，蚀刻第一区域以形成具有第一深度的空腔， 光致抗蚀剂的一部分以暴露衬底的附加区域，并且蚀刻该腔以暴露结构中的第一导体和附加区域以暴露该结构中的第二导体。

公开(公告)号：US20100289144A1

公开(公告)日：2010-11-18

申请号：US12465839

申请日：2009-05-14

申请人： Mukta G. Farooq ,  Subramanian S. lyer

发明人： Mukta G. Farooq ,  Subramanian S. lyer

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L24/94 ,  H01L21/76898 ,  H01L21/8221 ,  H01L24/16 ,  H01L24/28 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/13009 ,  H01L2224/13099 ,  H01L2224/80345 ,  H01L2224/80357 ,  H01L2224/80801 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/83201 ,  H01L2224/83801 ,  H01L2224/83894 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105

摘要： A method of making 3D integrated circuits and a 3D integrated circuit structure. There is a first semiconductor structure joined to a second semiconductor structure. Each semiconductor structure includes a semiconductor wafer, a front end of the line (FEOL) wiring on the semiconductor wafer, a back end of the line (BEOL) wiring on the FEOL wiring, an insulator layer on the BEOL wiring and a metallic layer on the insulator layer. The first semiconductor structure is aligned with the second semiconductor structure such that the metallic layers of each of the semiconductor structures face each other. The metallic layers of each of the semiconductor structures are in contact with and bonded to each other by a metal to metal bond wherein the bonded metallic layers form an electrically isolated layer.

摘要翻译： 制作3D集成电路和3D集成电路结构的方法。 连接到第二半导体结构的第一半导体结构。 每个半导体结构包括半导体晶片，半导体晶片上的线的前端（FEOL）布线，FEOL布线上的线的后端（BEOL）布线，BEOL布线上的绝缘体层和金属层 绝缘体层。 第一半导体结构与第二半导体结构对准，使得每个半导体结构的金属层彼此面对。 每个半导体结构的金属层通过金属 - 金属键彼此接触并彼此结合，其中结合的金属层形成电隔离层。