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    Three-dimensional semiconductor memory device having compensating data skewing according to interlayer timing delay and method of de-skewing data therein
    121.
    发明授权
    Three-dimensional semiconductor memory device having compensating data skewing according to interlayer timing delay and method of de-skewing data therein 有权
    具有根据层间定时延迟的补偿数据偏移的三维半导体存储器件以及其中的数据失真的方法

    公开(公告)号：US08917564B2

    公开(公告)日：2014-12-23

    申请号：US13937367

    申请日：2013-07-09

    申请人： Samsung Electronics Co., Ltd.

    发明人： Hak-Soo Yu ,  Sang-Bo Lee ,  Hong-Sun Hwang ,  Dong-Hyun Sohn

    IPC分类号： G11C7/00 ,  G11C5/02 ,  G11C5/06 ,  G11C8/14 ,  G11C8/18 ,  G11C13/00 ,  G11C29/02 ,  G11C29/50 ,  G11C7/22

    CPC分类号： G11C5/02 ,  G11C5/063 ,  G11C7/222 ,  G11C8/14 ,  G11C8/18 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0061 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50012 ,  G11C2213/71

    摘要： A semiconductor memory device having a 3D stacked structure includes: a first semiconductor area with a stacked structure of a first layer having first data and a second layer having second data; a first line for delivering an access signal for accessing the first semiconductor area; and a second line for outputting the first and/or second data from the first semiconductor area, wherein access timings of accessing the first and second layers are controlled so that a first time delay from the delivery of the access signal to the first layer to the output of the first data is substantially identical to a second time delay from the delivery of the access signal to the second layer to the output of the second data, thereby compensating for skew according to an inter-layer timing delay and thus performing a normal operation. Accordingly, the advantage of high-integration according to a stacked structure can be maximized by satisfying data input/output within a predetermined standard.

    摘要翻译： 具有3D堆叠结构的半导体存储器件包括：具有第一层的层叠结构的第一半导体区域和具有第二数据的第二层; 用于传送访问所述第一半导体区域的访问信号的第一行; 以及用于从第一半导体区域输出第一和/或第二数据的第二行，其中控制访问第一和第二层的访问定时，以便从接收信号传送到第一层到第一层的第一时间延迟 第一数据的输出与从接收信号传送到第二层到第二数据的输出的第二时间延迟基本相同，从而根据层间定时延迟补偿偏移，从而执行正常操作 。 因此，通过满足预定标准中的数据输入/输出，可以最大化根据堆叠结构的高集成度的优点。

    Non-volatile memory device
    123.
    发明授权
    Non-volatile memory device 有权
    非易失性存储器件

    公开(公告)号：US08867299B2

    公开(公告)日：2014-10-21

    申请号：US13488207

    申请日：2012-06-04

    申请人： Je Il Ryu ,  Duck Ju Kim

    发明人： Je Il Ryu ,  Duck Ju Kim

    IPC分类号： G11C11/00 ,  G11C8/14

    CPC分类号： G11C8/14

    摘要： A non-volatile memory device includes a plurality of memory blocks, first block switches configured to correspond to the respective odd-numbered memory blocks of the plurality of memory blocks and couple the word lines of the odd-numbered memory blocks and first local lines, second block switches configured to correspond to the respective even-numbered memory blocks of the plurality of memory blocks and couple the word lines of the even-numbered memory blocks and second local lines, a local line switch unit configured to selectively couple the first local lines or the second local lines and global word lines, and a high voltage generator configured to supply operating voltages to the global word lines.

    摘要翻译： 非易失性存储器件包括多个存储器块，第一块开关被配置为对应于多个存储器块中的各个奇数存储块并且耦合奇数存储器块和第一局部线的字线， 第二块开关，被配置为对应于所述多个存储器块中的相应的偶数存储块，并且耦合所述偶数存储块和第二本地线的字线;局部线路开关单元，被配置为选择性地耦合所述第一本地线 或第二本地线路和全局字线，以及被配置为向全局字线提供工作电压的高压发生器。

    Static RAM
    124.
    发明授权
    Static RAM 有权
    静态RAM

    公开(公告)号：US08797786B2

    公开(公告)日：2014-08-05

    申请号：US13226726

    申请日：2011-09-07

    申请人： Shinichi Moriwaki

    发明人： Shinichi Moriwaki

    IPC分类号： G11C11/00 ,  G11C11/413 ,  G11C11/412 ,  G11C11/41 ,  G11C11/418 ,  G11C8/08 ,  G11C11/419 ,  G11C7/18 ,  G11C8/14

    CPC分类号： G11C11/413 ,  G11C7/18 ,  G11C8/08 ,  G11C8/14 ,  G11C11/41 ,  G11C11/412 ,  G11C11/418 ,  G11C11/419

    摘要： A static RAM includes a plurality of word lines, a plurality of global bit line pairs, a plurality of static-type memory cells, a plurality of sense amplifiers, a plurality of local bit line pairs provided in correspondence with each global bit line pair, and a plurality of global switches, wherein the plurality of static-type memory cells is connected to the corresponding local bit line pair in response to a row selection signal, and at the time of read, the row selection signal is applied to the word line and after the corresponding local bit line pair is brought into a state corresponding to contents stored in the memory cell, application of the row selection signal is stopped and then the corresponding global switch is brought into a connection state and after changing the state of the global bit line pair, the corresponding sense amplifier is operated.

    摘要翻译： 静态RAM包括多个字线，多个全局位线对，多个静态型存储单元，多个读出放大器，与每个全局位线对对应地提供的多个局部位线对， 以及多个全局开关，其中响应于行选择信号将多个静态型存储单元连接到对应的本地位线对，并且在读取时，行选择信号被施加到字线 并且在对应的本地位线对进入与存储单元中存储的内容相对应的状态之后，停止施加行选择信号，然后将相应的全局开关变为连接状态，并且在改变全局的状态之后 位线对，相应的读出放大器工作。

    Multi-column addressing mode memory system including an integrated circuit memory device
    125.
    发明授权
    Multi-column addressing mode memory system including an integrated circuit memory device 有权
    多列寻址模式存储器系统，包括集成电路存储器件

    公开(公告)号：US08154947B2

    公开(公告)日：2012-04-10

    申请号：US13239846

    申请日：2011-09-22

    申请人： Frederick A. Ware ,  Lawrence Lai ,  Chad A. Bellows ,  Wayne S. Richardson

    发明人： Frederick A. Ware ,  Lawrence Lai ,  Chad A. Bellows ,  Wayne S. Richardson

    IPC分类号： G11C8/14 ,  G06F5/76

    CPC分类号： G11C8/10 ,  G11C8/12 ,  G11C8/16

    摘要： A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.

    摘要翻译： 存储器系统包括主设备，诸如图形控制器或处理器，以及以双列寻址模式可操作的集成电路存储器件。 集成电路存储器件包括一个接口和列解码器，以访问一行存储单元或存储体中的一页。 在第一操作模式期间，响应于第一列地址可访问第一存储体中的第一行存储单元。 在第二操作模式期间，响应于列周期时间间隔期间的第二列地址，可访问第一行存储单元中的第一多个存储单元。 响应于列周期时间间隔期间的第三列地址，可访问第一行存储单元中的第二多个存储单元。 第一和第二多个存储单元可以从该接口同时访问。

    Standby current erasion circuit of DRAM
    126.
    发明授权
    Standby current erasion circuit of DRAM 有权
    DRAM的待机电流擦除电路

    公开(公告)号：US07652290B2

    公开(公告)日：2010-01-26

    申请号：US10232460

    申请日：2002-08-30

    申请人： Yu-Chang Lin

    发明人： Yu-Chang Lin

    IPC分类号： H01L27/108 ,  G11C29/04 ,  G11C29/12 ,  G11C29/50 ,  G11C8/08 ,  G11C8/10 ,  G11C8/14 ,  G11C7/12 ,  G11C7/18

    CPC分类号： G11C11/4085 ,  G11C2207/2227

    摘要： The present invention discloses a standby current erasion circuit applied in DRAM, which improves prior art word line driving circuit to have the word line voltage outputted in standby mode be equal to the bit line voltage, thereby the short DC standby current between the word line and bit line can be erased.

    摘要翻译： 本发明公开了一种应用在DRAM中的待机电流擦除电路，其改进了现有技术的字线驱动电路，使待机模式下输出的字线电压等于位线电压，从而在字线和 位线可以被擦除。

    Phase change random access memory (PRAM) device
    127.
    发明授权
    Phase change random access memory (PRAM) device 有权
    相变随机存取存储器（PRAM）设备

    公开(公告)号：US07639558B2

    公开(公告)日：2009-12-29

    申请号：US11315347

    申请日：2005-12-23

    申请人： Beak-hyung Cho ,  Kwang-jin Lee ,  Mu-hui Park

    发明人： Beak-hyung Cho ,  Kwang-jin Lee ,  Mu-hui Park

    IPC分类号： G11C8/08 ,  G11C8/14

    CPC分类号： G11C11/5678 ,  G11C7/12 ,  G11C13/0004 ,  G11C13/0028 ,  G11C2213/72

    摘要： A phase change memory device has a word line driver layout which allows for a reduction in the size a core area of the device. In one aspect, phase change memory device includes a plurality of memory cell blocks sharing a word line, and a plurality of word line drivers driving the word line. Each of the word line drivers includes a precharge device for precharging the word line and a discharge device for discharging the word line, and where the precharge device and the discharge device are alternately located between the plurality of memory cell blocks.

    摘要翻译： 相变存储器件具有字线驱动器布局，其允许减小器件的核心区域的尺寸。 一方面，相变存储器件包括共享字线的多个存储单元块和驱动该字线的多个字线驱动器。 每个字线驱动器包括用于对字线预充电的预充电装置和用于放电字线的放电装置，并且其中预充电装置和放电装置交替地位于多个存储单元块之间。

    Semiconductor memory device capable of operating at high speed
    128.
    发明授权
    Semiconductor memory device capable of operating at high speed 失效
    能够高速运转的半导体存储器件

    公开(公告)号：US07095673B2

    公开(公告)日：2006-08-22

    申请号：US11087600

    申请日：2005-03-24

    申请人： Yukihiro Fujimoto

    发明人： Yukihiro Fujimoto

    IPC分类号： G11C8/14

    CPC分类号： G11C11/413 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/12 ,  G11C7/18 ,  G11C2207/002

    摘要： A plurality of sub-arrays include a plurality of memory elements. First bit line pairs are connected to a plurality of memory elements provided in each of the sub-arrays. Second bit line pairs are provided so as to correspond to a plurality of sub-arrays. The first bit line pairs supply signals to the second bit line pairs. The second bit line pairs are operated at a lower frequency than the first bit line pairs.

    摘要翻译： 多个子阵列包括多个存储元件。 第一位线对被连接到设置在每个子阵列中的多个存储元件。 提供第二位线对以对应于多个子阵列。 第一位线对将信号提供给第二位线对。 第二位线对以比第一位线对更低的频率操作。

    Method and system for optimizing the number of word line segments in a segmented MRAM array
    129.
    发明申请
    Method and system for optimizing the number of word line segments in a segmented MRAM array 失效
    用于优化分段MRAM阵列中字线段数量的方法和系统

    公开(公告)号：US20050276100A1

    公开(公告)日：2005-12-15

    申请号：US10865717

    申请日：2004-06-09

    申请人： Hsu Yang ,  Xizeng Shi ,  Po-Kang Wang ,  Bruce Yang

    发明人： Hsu Yang ,  Xizeng Shi ,  Po-Kang Wang ,  Bruce Yang

    IPC分类号： G06F12/00 ,  G11C8/14 ,  G11C11/14 ,  G11C11/15

    CPC分类号： G11C11/15 ,  G11C8/14

    摘要： A method and system for programming and reading a magnetic memory is disclosed. The magnetic memory includes a plurality of selectable word line segments and a plurality of magnetic storage cells corresponding to each word line segment. The method and system include reading the magnetic storage cells corresponding to a word line segment to determine a state of each magnetic storage cell. In one aspect, the method and system also include utilizing at least one storage for storing a state of each of the magnetic storage cells determined during a read operation made during a write operation. The method and system also include writing data to a portion of the magnetic cells corresponding to the word line segment after the reading. The method and system also include rewriting the state to each of a remaining portion of the magnetic storage cells corresponding to the word line segment at substantially the same time as the portion of the magnetic cells are written.

    摘要翻译： 公开了一种用于编程和读取磁存储器的方法和系统。 磁存储器包括多个可选字线段和对应于每个字线段的多个磁存储单元。 该方法和系统包括读取对应于字线段的磁存储单元以确定每个磁存储单元的状态。 一方面，该方法和系统还包括利用至少一个存储器来存储在写入操作期间进行的读取操作期间确定的每个磁存储单元的状态。 该方法和系统还包括在读取之后将数据写入对应于字线段的磁性单元的一部分。 所述方法和系统还包括将所述状态重写为与写入所述磁性单元的所述部分基本相同的时间对应于所述字线段的所述磁存储单元的剩余部分。

    Nonvolatile ferroelectric memory device with split word lines
    130.
    发明申请
    Nonvolatile ferroelectric memory device with split word lines 有权

    公开(公告)号：US20050237784A1

    公开(公告)日：2005-10-27

    申请号：US11167854

    申请日：2005-06-28

    申请人： Hee-Bok Kang

    发明人： Hee-Bok Kang

    IPC分类号： G11C8/14 ,  G11C11/22 ,  G11C19/08

    CPC分类号： G11C8/14 ,  G11C11/22

    摘要： The present invention relates to a memory device; and, more particularly, to a cell array of a nonvolatile ferroelectric memory device and an apparatus and a method for driving such a cell array. The nonvolatile ferroelectric memory device according to the present invention includes: a cell array region having first and second cell array blocks which are adjacent to each other and independently operate; a first drive region being adjacent to the first cell array block in the cell array region in order to drive first split words line which operate as plate lines of the first cell array block and word lines of the second cell array block; and a second drive region being adjacent to the second cell array block in the cell array region in order to drive first split word lines which operate as plate lines of the second cell array block and word lines of the first cell array block, wherein each of the first and second drive regions includes a plurality of split word line drivers and wherein each of the split word line drivers is connected to the plate lines of the first and second cell array blocks correspondent thereto.