公开(公告)号：US06897009B2

公开(公告)日：2005-05-24

申请号：US10148303

申请日：2000-11-29

Applicant: Alan T. Johnson, Jr. ,  Marko Radosavljevic ,  Jacques Lefebvre

Inventor： Alan T. Johnson, Jr. ,  Marko Radosavljevic ,  Jacques Lefebvre

IPC: H01L21/033 ,  H01L21/3213 ,  H01L51/00 ,  H01L51/30 ,  H01L51/40 ,  G03F7/00

CPC classification number: H01L21/32139 ,  B82Y10/00 ,  H01L21/0334 ,  H01L51/0021 ,  H01L51/0048 ,  H01L51/0052 ,  Y10S977/75 ,  Y10S977/752

Abstract: A shadow mask method to fabricate electrodes with nanometer scale separation utilizes nanotubes (NTs). Metal wires with gaps are made by incorporating multi-wall carbon nanotubes (MWNTs) or single-wall carbon nanotubes (SWNTs) (or bundles thereof) into a tri-layer electron beam lithography process. The simple, highly controllable, and scaleable method can be used to make gaps with widths between 1 and 100 nm. Electronic transport measurements performed on individual SWNTs bridge nanogaps smaller than 30 nm. Metallic SWNTs exhibit quantum dot behavior with an 80 meV charging energy and a 20 meV energy level splitting. Semiconducting SWNTs show an anomalous field effect transistor behavior.

Abstract translation: 用纳米尺度分离制造电极的荫罩方法使用纳米管（NT）。 具有间隙的金属线通过将多壁碳纳米管（MWNT）或单壁碳纳米管（SWNT）（或其束）结合到三层电子束光刻工艺中而制成。 可以使用简单，高度可控和可扩展的方法来形成宽度在1和100nm之间的间隙。 在单个SWNT上执行的电子传输测量桥接小于30nm的纳米膜。 金属SWNTs具有量子点行为，具有80meV的充电能量和20meV的能级分裂。 半导体SWNTs显示出异常的场效应晶体管行为。

公开(公告)号：US10290614B2

公开(公告)日：2019-05-14

申请号：US13977195

申请日：2011-12-19

Applicant: Han Wui Then ,  Robert Chau ,  Valluri Rao ,  Niloy Mukherjee ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Gilbert Dewey ,  Jack Kavalieros

Inventor： Han Wui Then ,  Robert Chau ,  Valluri Rao ,  Niloy Mukherjee ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Gilbert Dewey ,  Jack Kavalieros

IPC: H01L25/00 ,  H01L25/07 ,  H01L27/06 ,  H01L29/20 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L29/423 ,  H01L29/778 ,  H01L21/8252 ,  H01L21/8258

Abstract: System on Chip (SoC) solutions integrating an RFIC with a PMIC using a transistor technology based on group III-nitrides (III-N) that is capable of achieving high Ft and also sufficiently high breakdown voltage (BV) to implement high voltage and/or high power circuits. In embodiments, the III-N transistor architecture is amenable to scaling to sustain a trajectory of performance improvements over many successive device generations. In embodiments, the III-N transistor architecture is amenable to monolithic integration with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. Planar and non-planar HEMT embodiments having one or more of recessed gates, symmetrical source and drain, regrown source/drains are formed with a replacement gate technique permitting enhancement mode operation and good gate passivation.

公开(公告)号：US09711591B2

公开(公告)日：2017-07-18

申请号：US13997607

申请日：2011-12-28

Applicant: Niloy Mukherjee ,  Matthew V. Metz ,  James M. Powers ,  Van H. Le ,  Benjamin Chu-Kung ,  Mark R. Lemay ,  Marko Radosavljevic ,  Niti Goel ,  Loren Chow ,  Peter G. Tolchinsky ,  Jack T. Kavalieros ,  Robert S. Chau

Inventor： Niloy Mukherjee ,  Matthew V. Metz ,  James M. Powers ,  Van H. Le ,  Benjamin Chu-Kung ,  Mark R. Lemay ,  Marko Radosavljevic ,  Niti Goel ,  Loren Chow ,  Peter G. Tolchinsky ,  Jack T. Kavalieros ,  Robert S. Chau

IPC: H01L21/02 ,  H01L29/06

CPC classification number: H01L29/06 ,  H01L21/0237 ,  H01L21/0245 ,  H01L21/02455 ,  H01L21/02494 ,  H01L21/02502 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02587 ,  H01L21/0259 ,  H01L21/02617 ,  H01L21/02636 ,  H01L21/02658 ,  H01L21/02664

Abstract: Methods of forming hetero-layers with reduced surface roughness and bulk defect density on non-native surfaces and the devices formed thereby are described. In one embodiment, the method includes providing a substrate having a top surface with a lattice constant and depositing a first layer on the top surface of the substrate. The first layer has a top surface with a lattice constant that is different from the first lattice constant of the top surface of the substrate. The first layer is annealed and polished to form a polished surface. A second layer is then deposited above the polished surface.

公开(公告)号：US09583574B2

公开(公告)日：2017-02-28

申请号：US13631514

申请日：2012-09-28

Applicant: Sansaptak Dasgupta ,  Han Wui Then ,  Niloy Mukherjee ,  Marko Radosavljevic ,  Robert S. Chau

Inventor： Sansaptak Dasgupta ,  Han Wui Then ,  Niloy Mukherjee ,  Marko Radosavljevic ,  Robert S. Chau

IPC: H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L29/778 ,  H01L29/423

CPC classification number: H01L29/7787 ,  H01L23/535 ,  H01L29/04 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66545

Abstract: Embodiments include epitaxial semiconductor stacks for reduced defect densities in III-N device layers grown over non-III-N substrates, such as silicon substrates. In embodiments, a metamorphic buffer includes an AlxIn1-xN layer lattice matched to an overlying GaN device layers to reduce thermal mismatch induced defects. Such crystalline epitaxial semiconductor stacks may be device layers for HEMT or LED fabrication, for example. System on Chip (SoC) solutions integrating an RFIC with a PMIC using a transistor technology based on group III-nitrides (III-N) capable of achieving high Ft and also sufficiently high breakdown voltage (BV) to implement high voltage and/or high power circuits may be provided on the semiconductor stacks in a first area of the silicon substrate while silicon-based CMOS circuitry is provided in a second area of the substrate.

Abstract translation: 实施例包括用于在诸如硅衬底的非III-N衬底上生长的III-N器件层中的缺陷密度降低的外延半导体堆叠。 在实施例中，变质缓冲器包括与上覆GaN器件层匹配的Al x In 1-x N层晶格以减少热失配引起的缺陷。 这种结晶外延半导体叠层可以是用于例如HEMT或LED制造的器件层。 使用基于能够实现高Ft的III族氮化物（III-N）的晶体管技术并且还具有足够高的击穿电压（BV）来实现高电压和/或高电平的片上系统（SoC）解决方案集成RFIC与PMIC 电源电路可以设置在硅衬底的第一区域中的半导体堆叠上，而硅基CMOS电路设置在衬底的第二区域中。

公开(公告)号：US09461160B2

公开(公告)日：2016-10-04

申请号：US13976837

申请日：2011-12-19

Applicant: Han Wui Then ,  Robert Chau ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Marko Radosavljevic

Inventor： Han Wui Then ,  Robert Chau ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Marko Radosavljevic

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/78 ,  H01L29/20

CPC classification number: H01L29/7787 ,  G06F1/1633 ,  G06F1/189 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/0254 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786 ,  H01L29/7789 ,  H01L29/785 ,  H03F3/195 ,  H03F3/213 ,  H03F2200/451

Abstract: Transistors for high voltage and high frequency operation. A non-planar, polar crystalline semiconductor body having a top surface disposed between first and second opposite sidewalls includes a channel region with a first crystalline semiconductor layer disposed over the first and second sidewalls. The first crystalline semiconductor layer is to provide a two dimensional electron gas (2DEG) within the channel region. A gate structure is disposed over the first crystalline semiconductor layer along at least the second sidewall to modulate the 2DEG. First and second sidewalls of the non-planar polar crystalline semiconductor body may have differing polarity, with the channel proximate to a first of the sidewalls. The gate structure may be along a second of the sidewalls to gate a back barrier. The polar crystalline semiconductor body may be a group III-nitride formed on a silicon substrate with the (1010) plane on a (110) plane of the silicon.

Abstract translation: 用于高压和高频工作的晶体管。 具有设置在第一和第二相对侧壁之间的顶表面的非平面极性晶体半导体本体包括具有设置在第一和第二侧壁上的第一晶体半导体层的沟道区域。 第一晶体半导体层是在沟道区内提供二维电子气（2DEG）。 栅极结构沿至少第二侧壁设置在第一晶体半导体层上方，以调制2DEG。 非平面极性结晶半导体主体的第一和第二侧壁可具有不同的极性，其中通道靠近第一侧壁。 栅极结构可以沿着侧壁中的第二侧面以栅极背栅。 极性结晶半导体体可以是在硅衬底上形成的III族氮化物，其中（1010）面在硅的（110）平面上。

公开(公告)号：US09343574B2

公开(公告)日：2016-05-17

申请号：US14688410

申请日：2015-04-16

Applicant: Gilbert Dewey ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Niloy Mukherjee

Inventor： Gilbert Dewey ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Niloy Mukherjee

IPC: H01L29/00 ,  H01L29/78 ,  B82Y10/00 ,  H01L29/775 ,  H01L29/06 ,  H01L29/205 ,  H01L29/40 ,  H01L29/423 ,  H01L29/51 ,  H01L29/786 ,  H01L29/201 ,  B82Y99/00

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  B82Y99/00 ,  H01L29/0665 ,  H01L29/201 ,  H01L29/205 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/511 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78696

Abstract: Non-planar semiconductor devices having group III-V material active regions with multi-dielectric gate stacks are described. For example, a semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a three-dimensional group III-V material body with a channel region. A source and drain material region is disposed above the three-dimensional group III-V material body. A trench is disposed in the source and drain material region separating a source region from a drain region, and exposing at least a portion of the channel region. A gate stack is disposed in the trench and on the exposed portion of the channel region. The gate stack includes first and second dielectric layers and a gate electrode.

Abstract translation: 描述具有多电介质栅叠层的具有III-V族材料的区域的非平面半导体器件。 例如，半导体器件包括设置在衬底上的异质结构。 异质结构包括具有沟道区的三维III-V族材料体。 源极和漏极材料区域设置在三维III-V族材料体上方。 在源极和漏极材料区域中布置沟槽，其将源极区域与漏极区域分离，并且暴露沟道区域的至少一部分。 栅极堆叠设置在沟槽中和沟道区域的暴露部分上。 栅极堆叠包括第一和第二电介质层和栅电极。

公开(公告)号：US20150206796A1

公开(公告)日：2015-07-23

申请号：US14162717

申请日：2014-01-23

Applicant: Sansaptak Dasgupta ,  Han Wui Then ,  Sanaz K. Gardner ,  Seung Hoon Sung ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Sherry R. Taft ,  Ravi Pillarisetty ,  Robert S. Chau

Inventor： Sansaptak Dasgupta ,  Han Wui Then ,  Sanaz K. Gardner ,  Seung Hoon Sung ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Sherry R. Taft ,  Ravi Pillarisetty ,  Robert S. Chau

IPC: H01L21/768 ,  H01L21/762 ,  H01L21/02

CPC classification number: H01L29/2003 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/8258 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0684

Abstract: A trench comprising a portion of a substrate is formed. A nucleation layer is deposited on the portion of the substrate within the trench. A III-N material layer is deposited on the nucleation layer. The III-N material layer is laterally grown over the trench. A device layer is deposited on the laterally grown III-N material layer. A low defect density region is obtained on the laterally grown material and is used for electronic device fabrication of III-N materials on Si substrates.

Abstract translation: 形成包括基板的一部分的沟槽。 成核层沉积在沟槽内的衬底部分上。 在成核层上沉积III-N材料层。 在沟槽上横向生长III-N材料层。 器件层沉积在横向生长的III-N材料层上。 在横向生长的材料上获得低缺陷密度区域，并用于Si衬底上的III-N材料的电子器件制造。

公开(公告)号：US20150187924A1

公开(公告)日：2015-07-02

申请号：US14141304

申请日：2013-12-26

Applicant: Sansaptak Dasgupta ,  Han Wui Then ,  Marko Radosavljevic ,  Sanaz K. Gardner ,  Seung Hoon Sung ,  Benjamin Chu-Kung ,  Robert S. Chau

Inventor： Sansaptak Dasgupta ,  Han Wui Then ,  Marko Radosavljevic ,  Sanaz K. Gardner ,  Seung Hoon Sung ,  Benjamin Chu-Kung ,  Robert S. Chau

IPC: H01L29/778 ,  H01L21/306 ,  H01L29/66

CPC classification number: H01L29/7783 ,  H01L21/30612 ,  H01L21/30617 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7786

Abstract: Transistors or transistor layers include an InAlN and AlGaN bi-layer capping stack on a 2DEG GaN channel, such as for GaN MOS structures on Si substrates. The GaN channel may be formed in a GaN buffer layer or stack, to compensate for the high crystal structure lattice size and coefficient of thermal expansion mismatch between GaN and Si. The bi-layer capping stack an upper InAlN layer on a lower AlGaN layer to induce charge polarization in the channel, compensate for poor composition uniformity (e.g., of Al), and compensate for rough surface morphology of the bottom surface of the InAlN material. It may lead to a sheet resistance between 250 and 350 ohms/sqr. It may also reduce bowing of the GaN on Si wafers during growth of the layer of InAlN material, and provide a AlGaN setback layer for etching the InAlN layer in the gate region.

Abstract translation: 晶体管或晶体管层包括2DEG GaN沟道上的InAlN和AlGaN双层封装叠层，例如用于Si衬底上的GaN MOS结构。 GaN沟道可以形成在GaN缓冲层或堆叠中，以补偿GaN和Si之间的高晶格结构晶格尺寸和热膨胀失配系数。 双层封装在下AlGaN层上堆叠上InAlN层以在沟道中引起电荷极化，补偿较差的组成均匀性（例如Al），并补偿InAlN材料的底表面的粗糙表面形态。 它可能导致250和350欧姆/ sqr之间的薄层电阻。 还可以在InAlN材料层的生长期间减少Si晶片上的GaN的弯曲，并且提供用于蚀刻栅极区域中的InAlN层的AlGaN回填层。

公开(公告)号：US09018680B2

公开(公告)日：2015-04-28

申请号：US14340981

申请日：2014-07-25

Applicant: Gilbert Dewey ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Niloy Mukherjee

Inventor： Gilbert Dewey ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Niloy Mukherjee

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/78 ,  B82Y10/00 ,  H01L29/775 ,  H01L29/06 ,  H01L29/205 ,  H01L29/423 ,  H01L29/51 ,  H01L29/786 ,  B82Y99/00

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  B82Y99/00 ,  H01L29/0665 ,  H01L29/201 ,  H01L29/205 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/511 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78696

Abstract: Non-planar semiconductor devices having group III-V material active regions with multi-dielectric gate stacks are described. For example, a semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a three-dimensional group III-V material body with a channel region. A source and drain material region is disposed above the three-dimensional group III-V material body. A trench is disposed in the source and drain material region separating a source region from a drain region, and exposing at least a portion of the channel region. A gate stack is disposed in the trench and on the exposed portion of the channel region. The gate stack includes first and second dielectric layers and a gate electrode.

Abstract translation: 描述具有多电介质栅叠层的具有III-V族材料的区域的非平面半导体器件。 例如，半导体器件包括设置在衬底上的异质结构。 异质结构包括具有沟道区的三维III-V族材料体。 源极和漏极材料区域设置在三维III-V族材料体上方。 在源极和漏极材料区域中布置沟槽，其将源极区域与漏极区域分离，并且暴露沟道区域的至少一部分。 栅极堆叠设置在沟槽中和沟道区域的暴露部分上。 栅极堆叠包括第一和第二电介质层和栅电极。

公开(公告)号：US08883573B2

公开(公告)日：2014-11-11

申请号：US13563456

申请日：2012-07-31

Applicant: Uday Shah ,  Benjamin Chu-Kung ,  Been-Yih Jin ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Willy Rachmady

Inventor： Uday Shah ,  Benjamin Chu-Kung ,  Been-Yih Jin ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Willy Rachmady

IPC: H01L21/335 ,  H01L29/06 ,  H01L29/78 ,  H01L21/02 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/762 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78 ,  H01L29/78696 ,  H01L2221/1094

Abstract: The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present disclosure relates to forming an isolated nanowire, wherein isolation structure adjacent the nanowire provides a substantially level surface for the formation of microelectronic structures thereon.

Abstract translation: 本公开涉及制造微电子器件的领域。 在至少一个实施方案中，本公开涉及形成分离的纳米线，其中与纳米线相邻的隔离结构提供用于在其上形成微电子结构的基本水平的表面。