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    3D semiconductor device and structure including power distribution grids
    132.
    发明授权
    3D semiconductor device and structure including power distribution grids 有权

    公开(公告)号：US12249538B2

    公开(公告)日：2025-03-11

    申请号：US18228907

    申请日：2023-08-01

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak Sekar

    IPC: H01L21/74

    Abstract: A 3D device includes a first level including a first single crystal layer with control circuitry, where the control circuitry includes first single crystal transistors; a first metal layer atop first single crystal layer; a second metal layer atop the first metal layer; a third metal layer atop the second metal layer; second level (includes a plurality of second transistors, including metal gate) atop the third metal layer; a fourth metal layer above the one second level; a fifth metal layer atop the fourth metal layer, where the second level includes at least one first oxide layer overlaid by a transistor layer and then overlaid by a second oxide layer; a global power distribution grid including the fifth metal layer; a local power distribution grid, the thickness of the fifth metal layer is at least 50% greater than the thickness of the second metal layer, a layer deposited by ALD.

    3D SEMICONDUCTOR DEVICES AND STRUCTURES WITH SLITS
    134.
    发明申请
    3D SEMICONDUCTOR DEVICES AND STRUCTURES WITH SLITS 有权

    公开(公告)号：US20240404600A1

    公开(公告)日：2024-12-05

    申请号：US18800057

    申请日：2024-08-10

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Eli Lusky

    IPC: G11C16/10 ,  H10B20/25 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

    Abstract: A semiconductor device including: a first level including memory control circuits (include a plurality of refresh circuits for the memory units) which include first transistors; a second level including a first array of memory cells including second transistors self-aligned to at least one of the third transistors; a third level disposed on top of the second level disposed on top of first level, the third level including a second array of memory cells including third transistors; a fourth level disposed on top of the third level, the fourth level including a third array of memory cells including fourth transistors, second level is bonded to the first level, a plurality of slits disposed through the second level, the third level, and the fourth level, the slits enable gate replacement of a plurality of the third transistors, where the second array of memory cells include a plurality of independently controlled memory units.

    3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH CONNECTION PATHS
    135.
    发明申请
    3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH CONNECTION PATHS 有权

    公开(公告)号：US20240379624A1

    公开(公告)日：2024-11-14

    申请号：US18779059

    申请日：2024-07-21

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Brian Cronquist

    IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L23/50 ,  H01L25/00 ,  H01L27/06

    Abstract: A 3D semiconductor device, the device including: a first level, where the first level includes a first layer, the first layer including first transistors, and where the first level includes a second layer, the second layer including first interconnections; a second level overlaying the first level, where the second level includes a plurality of second transistors, where the second level includes a third layer, the third layer including first conductive lines; a third level overlaying the second level, where the third level includes a plurality of third transistors, where the third level includes a fourth layer, the fourth layer including second conductive lines; and a plurality of connection paths, where the plurality of connection paths provides electrical connections at least from a plurality of the first transistors to the plurality of third transistors, and where the first level includes at least one voltage regulator.

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