公开(公告)号：US20160043237A1

公开(公告)日：2016-02-11

申请号：US14821969

申请日：2015-08-10

Applicant: Infineon Technologies AG

Inventor： Holger Hüsken ,  Anton Mauder ,  Hans-Joachim Schulze ,  Wolfgang Rösner ,  Holger Schulze

IPC: H01L29/872 ,  H01L29/417

CPC classification number: H01L29/872 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/32 ,  H01L29/36 ,  H01L29/417 ,  H01L29/45 ,  H01L29/47 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/868

Abstract: A semiconductor device includes at least one first contact region of a vertical device between a semiconductor substrate and an electrically conductive structure arranged adjacent to the semiconductor substrate, and at least one second contact region of the vertical device between the semiconductor substrate of the semiconductor device and the electrically conductive structure. The at least one first contact region is arranged adjacent to the at least one second contact region. The electrically conductive structure includes a first electrically conductive material in contact with the semiconductor substrate in an area of the at least one first contact region and a second electrically conductive material in contact with the semiconductor substrate in an area of the at least one second contact region, so that a first contact characteristic within the at least one first contact region differs from a second contact characteristic within the at least one second contact region.

Abstract translation: 半导体器件包括在半导体衬底和邻近半导体衬底布置的导电结构之间的垂直器件的至少一个第一接触区域，以及垂直器件的至少一个第二接触区域，位于半导体器件的半导体衬底和 导电结构。 所述至少一个第一接触区域布置成与所述至少一个第二接触区域相邻。 所述导电结构包括在所述至少一个第一接触区域的区域中与所述半导体衬底接触的第一导电材料和在所述至少一个第二接触区域的区域中与所述半导体衬底接触的第二导电材料 使得所述至少一个第一接触区域内的第一接触特性与所述至少一个第二接触区域内的第二接触特性不同。

公开(公告)号：US09231581B2

公开(公告)日：2016-01-05

申请号：US14551632

申请日：2014-11-24

Applicant: Infineon Technologies AG

Inventor： Frank Pfirsch ,  Dorothea Werber ,  Anton Mauder ,  Carsten Schaeffer

IPC: H01L29/66 ,  H01L29/739 ,  H03K17/66 ,  H01L29/40 ,  H01L29/06 ,  H01L29/08 ,  H03K3/01

CPC classification number: H03K17/127 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/404 ,  H01L29/407 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/7397 ,  H03K3/01 ,  H03K17/66

Abstract: According to an embodiment of a method, a semiconductor device is operated in a reverse biased unipolar mode before operating the semiconductor device in an off-state in a forward biased mode. The semiconductor device includes at least one floating parasitic region disposed outside a cell region of the device.

Abstract translation: 根据一种方法的实施例，半导体器件在反向偏置单极模式下工作，然后在正向偏置模式中将半导体器件操作为截止状态。 半导体器件包括设置在器件的单元区域外的至少一个浮置寄生区域。

公开(公告)号：US20150236142A1

公开(公告)日：2015-08-20

申请号：US14180924

申请日：2014-02-14

Applicant: Infineon Technologies AG

Inventor： Johannes Georg Laven ,  Hans-Joachim Schulze ,  Anton Mauder ,  Erich Griebl

IPC: H01L29/739 ,  H01L21/306 ,  H01L21/324 ,  H01L21/225 ,  H01L29/36 ,  H01L29/66 ,  H01L29/16 ,  H01L29/04 ,  H01L29/06 ,  H01L29/10 ,  H01L21/02 ,  H01L21/265

CPC classification number: H01L21/26513 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/02598 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/02642 ,  H01L21/02647 ,  H01L21/0265 ,  H01L21/02667 ,  H01L21/2251 ,  H01L21/2254 ,  H01L21/2257 ,  H01L21/26533 ,  H01L21/30604 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/3247 ,  H01L21/6835 ,  H01L23/544 ,  H01L29/04 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/36 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/8611 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A cavity is formed in a first semiconductor layer that is formed on a semiconducting base layer. The cavity extends from a process surface of the first semiconductor layer to the base layer. A recessed mask liner is formed on a portion of a sidewall of the cavity distant to the process surface or a mask plug is formed in a portion of the cavity distant do the process surface. A second semiconductor layer is grown by epitaxy on the process surface. The second semiconductor layer spans the cavity.

Abstract translation: 在形成在半导体基底层上的第一半导体层中形成空腔。 空腔从第一半导体层的工艺表面延伸到基层。 凹陷的掩模衬垫形成在远离处理表面的空腔的侧壁的一部分上，或者在远离处理表面的空腔的一部分中形成掩模塞。 通过在工艺表面上外延生长第二半导体层。 第二半导体层跨越空腔。

公开(公告)号：US20150162418A1

公开(公告)日：2015-06-11

申请号：US14102290

申请日：2013-12-10

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Anton Mauder ,  Markus Zundel ,  Hans-Joachim Schulze ,  Franz Hirler ,  Hans Weber

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L29/06

CPC classification number: H01L29/66333 ,  H01L21/02118 ,  H01L21/0223 ,  H01L21/02238 ,  H01L21/02258 ,  H01L21/30604 ,  H01L21/76831 ,  H01L21/76898 ,  H01L29/0634 ,  H01L29/0661 ,  H01L29/402 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/861

Abstract: A method for forming a semiconductor device includes forming an electrical structure at a main surface of a semiconductor substrate and carrying out an anodic oxidation of a back side surface region of a back side surface of the semiconductor substrate to form an oxide layer at the back side surface of the semiconductor substrate.

Abstract translation: 一种形成半导体器件的方法包括在半导体衬底的主表面上形成电结构，并对半导体衬底的背面表面的背面表面区进行阳极氧化，以在后侧形成氧化物层 半导体衬底的表面。

公开(公告)号：US20140225125A1

公开(公告)日：2014-08-14

申请号：US13765102

申请日：2013-02-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Rudolf Berger ,  Hans-Joachim Schulze ,  Anton Mauder ,  Wolfgang Lehnert ,  Günther Ruhl ,  Roland Rupp

IPC: H01L29/16 ,  H01L23/29 ,  H01L21/56

CPC classification number: H01L29/1608 ,  H01L21/02002 ,  H01L21/2007 ,  H01L21/56 ,  H01L23/291 ,  H01L23/298 ,  H01L29/1075 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A composite wafer includes a substrate and a SiC-based functional layer. The substrate includes a porous carbon substrate core and an encapsulating layer encapsulating the substrate core. The SiC-based functional layer comprises, at an interface region with the encapsulating layer, at least one of: a carbide and a silicide formed by reaction of a portion of the SiC-based functional layer with a carbide-and-silicide-forming metal. An amount of the carbide-and-silicide-forming metal, integrated over the thickness of the functional layer, is 10−4 mg/cm2 to 0.1 mg/cm2.

Abstract translation: 复合晶片包括基板和SiC基功能层。 衬底包括多孔碳衬底芯和封装衬底芯的封装层。 所述SiC基功能层在与所述封装层的界面区域处包含以下中的至少一种：碳化物和由所述SiC基功能层的一部分与碳化物和硅化物形成金属反应形成的硅化物 。 在功能层的厚度上积分的碳化物和硅化物形成金属的量为10-4mg / cm 2至0.1mg / cm 2。

公开(公告)号：US20240063216A1

公开(公告)日：2024-02-22

申请号：US18364494

申请日：2023-08-03

Applicant: Infineon Technologies AG

Inventor： Digvijay Raghunathan ,  Anton Mauder

IPC: H01L27/06 ,  H01L29/861 ,  H01L29/739 ,  H01L29/78

CPC classification number: H01L27/0629 ,  H01L27/0664 ,  H01L29/8611 ,  H01L29/7398 ,  H01L29/7827 ,  H02M3/003

Abstract: A semiconductor device includes: a transistor formed in a first semiconductor layer stack; a diode formed in a second semiconductor layer stack, the diode including an anode metal layer; and a carrier. The transistor and the diode are mounted to the carrier. A terminal of the transistor is electrically connected to the carrier, and the anode metal layer is in direct contact with the carrier.

公开(公告)号：US11837528B2

公开(公告)日：2023-12-05

申请号：US17167242

申请日：2021-02-04

Applicant: Infineon Technologies AG

Inventor： Anton Mauder ,  Hans-Joachim Schulze

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L29/861 ,  H01L29/78 ,  H01L29/40 ,  H01L29/417 ,  H01L29/739

CPC classification number: H01L23/49513 ,  H01L21/4825 ,  H01L23/3121 ,  H01L23/49562 ,  H01L24/03 ,  H01L24/08 ,  H01L24/48 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/8611 ,  H01L2224/022 ,  H01L2224/0219 ,  H01L2224/02185 ,  H01L2224/03011 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/0603 ,  H01L2224/48111 ,  H01L2224/48237 ,  H01L2224/4903 ,  H01L2224/49111 ,  H01L2224/84815 ,  H01L2224/8592 ,  H01L2224/85815

Abstract: A method of manufacturing a semiconductor device includes: forming a base portion of a bonding pad on a semiconductor portion, the base portion further comprising a base layer; forming a main surface of the bonding pad, the main surface comprising a bonding region; bonding a bond wire or clip to the bonding region; and forming a supplemental structure directly on the base portion. The supplemental structure laterally adjoins the bond wire or clip or is laterally spaced apart from the bond wire or clip. A volume-related specific heat capacity of the supplemental structure is higher than a volume-related specific heat capacity of the base layer.

公开(公告)号：US20220262935A1

公开(公告)日：2022-08-18

申请号：US17668793

申请日：2022-02-10

Applicant: Infineon Technologies AG

Inventor： Hans-Juergen Thees ,  Alim Karmous ,  Anton Mauder

IPC: H01L29/739 ,  H03K17/567 ,  H02M1/08

Abstract: A voltage-controlled switching device includes a drain/drift region of a first conductivity type formed in a semiconductor portion. A channel region and the drain/drift region are in direct contact with each other. A source region of a second conductivity type and the channel region are in direct contact with each other. A gate electrode and the channel region are capacitively coupled and configured such that, in a an on-state of the voltage-controlled switching device, a first enhancement region of charge carriers corresponding to the first conductivity type forms in the channel region and band-to-band tunneling is facilitated between the source region and the first enhancement region.

公开(公告)号：US11302781B2

公开(公告)日：2022-04-12

申请号：US15951918

申请日：2018-04-12

Applicant: Infineon Technologies AG

Inventor： Joachim Weyers ,  Stefan Gamerith ,  Franz Hirler ,  Anton Mauder

IPC: H01L29/16 ,  H01L27/02 ,  H01L29/06

Abstract: A semiconductor device includes a semiconductor body having a first surface and a second surface opposite to the first surface. A transistor structure is formed is the semiconductor body. A trench structure extends from the first surface into the semiconductor body. An electrostatic discharge protection structure is accommodated in the trench structure. The electrostatic discharge protection structure includes a first terminal region and a second terminal region. A source contact structure at the first surface is electrically connected to source regions of the transistor structure and to the first terminal region. A gate contact structure at the first surface is electrically connected to a gate electrode of the transistor structure and to the second terminal region.

公开(公告)号：US11069626B2

公开(公告)日：2021-07-20

申请号：US16385337

申请日：2019-04-16

Applicant: Infineon Technologies AG

Inventor： Anton Mauder ,  Oliver Hellmund ,  Peter Irsigler ,  Hanno Melzner ,  Stefan Miethaner ,  Sebastian Schmidt ,  Hans-Joachim Schulze

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H01L23/00 ,  H01L25/07 ,  H01L23/29

Abstract: A molding compound and a semiconductor arrangement with a molding compound are disclosed. The molding compound includes a matrix and a filler including filler particles. The filler particles each include a core with an electrically conducting or a semiconducting material and an electrically insulating cover.