Patent search ap:("MICRON TECHNOLOGY Page INC.") AND inv:"Brent Keeth"

131.

发明申请
STACKED MEMORY ROUTING TECHNIQUES 审中-公开

公开(公告)号：US20200098730A1

公开(公告)日：2020-03-26

申请号：US16576197

申请日：2019-09-19

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth

IPC: H01L25/065 , H01L23/48 , H01L23/00 , H01L23/528 , H01L25/18 , H01L25/00

Abstract: Techniques for signal routing between a host and dynamic random-access memory (DRAM) are provided. In an example, a routing layer for a dynamic random-access memory die (DRAM can include multiple through silicon via (TSV) terminations configured to electrically couple with TSVs of the DRAM, an intermediate interface area, and multiple routing traces. the multiple TSV terminations can be arranged in multiple TSV areas. The multiple TSV areas can be arranged in two columns. The intermediate interface area can include multiple micro-pillar bump terminations configured to couple, via a micro-pillar bump, with corresponding micro-pillar bump terminations of a semiconductor interposer. The multiple routing traces can couple control TSV terminations of the multiple TSV areas with a corresponding micro-pillar bump termination of the intermediate interface.

132.

发明申请
SIGNAL DELIVERY IN STACKED DEVICE 审中-公开

公开(公告)号：US20200058621A1

公开(公告)日：2020-02-20

申请号：US16665923

申请日：2019-10-28

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth , Mark Hiatt , Terry R. Lee , Mark Tuttle , Rahul Advani , John F. Schreck

IPC: H01L25/065 , H01L23/66 , H01L23/50

Abstract: Some embodiments include apparatus, systems, and methods having a base, a first die, a second arranged in a stacked with the first die and the base, and a structure located in the stack and outside at least one of the first and second dice and configured to transfer signals between the base and at least one of the first and second dice.

133.

发明申请
FRAME PROTOCOL OF MEMORY DEVICE 审中-公开

公开(公告)号：US20190121775A1

公开(公告)日：2019-04-25

申请号：US15981703

申请日：2018-05-16

Applicant: Micron Technology, Inc.

Inventor： James Brian Johnson , Brent Keeth

IPC: G06F13/42 , G06F15/167

CPC classification number: G06F13/4243 , G06F15/167

Abstract: Techniques are described herein for a training procedure that identifies a frame boundary and generates a frame clock to identify the beginning and the end of a frame. After the frame training procedure is complete, a memory device may be configured to execute a frame synchronization procedure to identify the beginning of a frame based on the frame clock without the use of headers or other information within the frame during an active session of the memory device. During an activation time period after a power-up event, the memory device may initiate the frame training procedure. Once the frames are synchronized, the memory device may be configured to use that frame clock during an entire active session (e.g., until a power-down event) to identify the beginning of a frame as part of a frame synchronization procedure.

134.

发明申请
RECONFIGURABLE MEMORY ARCHITECTURES 审中-公开

公开(公告)号：US20190121560A1

公开(公告)日：2019-04-25

申请号：US15981708

申请日：2018-05-16

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth , James Brian Johnson

IPC: G06F3/06 , H01L25/065 , H01L23/538 , H01L25/18 , G11C11/4076 , H01L23/14 , G11C11/4093 , G11C11/4096 , G11C11/22 , G06F11/10

Abstract: Techniques are described herein for a reconfigurable memory device that is configurable based on the type of interposer used to couple the memory device with a host device. The reconfigurable memory device may include a plurality components for a plurality of configurations. Various components of the reconfigurable memory die may be activated/deactivated based on what type of interposer is used in the memory device. For example, if a first type of interposer is used (e.g., a high-density interposer), the data channel may be eight data pins wide. In contrast, if second type of interposer is used (e.g., an organic-based interposer), the data channel may be four data pins wide. As such, a reconfigurable memory device may include data pins and related drivers that are inactive in some configurations.

135.

发明授权
Apparatus and method of power transmission sensing for stacked devices 有权

公开(公告)号：US10170448B2

公开(公告)日：2019-01-01

申请号：US15372246

申请日：2016-12-07

Applicant: Micron Technology, Inc.

Inventor： Adam S. El-Mansouri , Fuad Badrieh , Brent Keeth

IPC: H01L25/065 , G05F1/10

Abstract: Apparatuses for supplying power supply voltage in a plurality of dies are described. An example apparatus includes: a circuit board; a regulator on the circuit board that regulates a first voltage; a semiconductor device on the circuit board that receives the first voltage through a power line in the circuit board. The semiconductor device includes: a substrate on the circuit board, stacked via conductive balls, that receives the first voltage from the power line via the conductive balls; a plurality of dies on the semiconductor device, stacked via bumps, each die including a first conductive via that receives the first voltage via the bumps; a plurality of pillars between adjacent dies and couple the first conductive vias of the adjacent dies; and a sense node switch circuit that selectively couples one first conductive via of one die among the plurality of dies to the regulator.

136.

发明授权
Resistive memory sensing 有权

公开(公告)号：US10062432B2

公开(公告)日：2018-08-28

申请号：US14719053

申请日：2015-05-21

Applicant: Micron Technology, Inc.

Inventor： D. V. Nirmal Ramaswamy , Gurtej S. Sandhu , Lei Bi , Adam D. Johnson , Brent Keeth , Alessandro Calderoni , Scott E. Sills

IPC: G11C13/00 , G11C11/16

CPC classification number: G11C13/004 , G11C11/1673 , G11C13/0069 , G11C2013/0047 , G11C2013/0057

Abstract: The present disclosure includes apparatuses and methods for sensing a resistive memory cell. A number of embodiments include performing a sensing operation on a memory cell to determine a current value associated with the memory cell, applying a programming signal to the memory cell, and determining a data state of the memory cell based on the current value associated with the memory cell before applying the programming signal and a current value associated with the memory cell after applying the programming signal.

137.

发明申请
Memory Cells and Memory Arrays 审中-公开

公开(公告)号：US20180061835A1

公开(公告)日：2018-03-01

申请号：US15664161

申请日：2017-07-31

Applicant: Micron Technology, Inc.

Inventor： Gloria Yang , Suraj J. Mathew , Raghunath Singanamalla , Vinay Nair , Scott J. Derner , Michael Amiel Shore , Brent Keeth , Fatma Arzum Simsek-Ege , Diem Thy N. Tran

IPC: H01L27/108 , H01L27/06 , H01L29/423 , H01L49/02 , H01L29/78

CPC classification number: H01L27/108 , G11C11/403 , H01L23/528 , H01L27/0688 , H01L28/90 , H01L29/0847 , H01L29/1037 , H01L29/42376 , H01L29/7827

Abstract: Some embodiments include a memory cell having first and second transistors, and a capacitor vertically displaced relative to the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes. Some embodiments include a memory cell having first and second transistors vertically displaced relative to one another, and a capacitor between the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes.

138.

发明申请
SYSTEM AND METHOD FOR DECODING COMMANDS BASED ON COMMAND SIGNALS AND OPERATING STATE 有权
Title translation: 基于命令信号和操作状态解码命令的系统和方法

公开(公告)号：US20170004872A1

公开(公告)日：2017-01-05

申请号：US15265677

申请日：2016-09-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： JEFFERY W. JANZEN , Brent Keeth , Jeffrey P. Wright , James S. Cullum

IPC: G11C11/4096 , G11C11/4091 , G11C11/406 , G11C11/408 , G11C11/4076

CPC classification number: G11C11/4096 , G11C7/1072 , G11C11/40611 , G11C11/4076 , G11C11/4087 , G11C11/4091

Abstract: A system and method for decoding command signals that includes a command decoder configured to generate internal control signals to perform an operation based on the command signals and an operating state. The same combination of command signals can request different commands depending on the operating state. A command is selected from a first set of operations according to the command signals when the memory system is in a first operating state and a command is selected from a second set of operations according to the command signals when the memory system is in a second operating state.

Abstract translation: 一种用于对命令信号进行解码的系统和方法，该系统和方法包括一个命令解码器，该命令解码器经配置以产生内部控制信号，以根据命令信号和操作状态执行操作。命令信号的相同组合可以根据操作状态请求不同的命令。当存储器系统处于第一操作状态时，根据命令信号从第一组操作中选择命令，并且当存储器系统处于第二操作时根据命令信号从第二组操作中选择命令州。