公开(公告)号：US09741867B2

公开(公告)日：2017-08-22

申请号：US15181621

申请日：2016-06-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi Kato ,  Jun Koyama

IPC: H01L29/04 ,  H04M1/00 ,  H01L29/786 ,  H01L27/06 ,  H01L27/12 ,  H04B1/40 ,  G06K19/077 ,  H01L29/10 ,  H01L23/66

CPC classification number: H01L29/78696 ,  G06K19/07749 ,  G06K19/07773 ,  H01L23/66 ,  H01L27/0688 ,  H01L27/1225 ,  H01L29/1033 ,  H01L29/7869 ,  H01L2223/6677 ,  H04B1/40 ,  Y02D70/00

Abstract: An object is to achieve low power consumption and a long lifetime of a semiconductor device having a wireless communication function. The object can be achieved in such a manner that a battery serving as a power supply source and a specific circuit are electrically connected to each other through a transistor in which a channel formation region is formed using an oxide semiconductor. The hydrogen concentration of the oxide semiconductor is lower than or equal to 5×1019 (atoms/cm3). Therefore, leakage current of the transistor can be reduced. As a result, power consumption of the semiconductor device in a standby state can be reduced. Further, the semiconductor device can have a long lifetime.

公开(公告)号：US09666614B2

公开(公告)日：2017-05-30

申请号：US14481458

申请日：2014-09-09

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei Yamazaki ,  Satoshi Murakami ,  Masahiko Hayakawa ,  Kiyoshi Kato ,  Mitsuaki Osame

IPC: H01L27/12 ,  G02F1/1362 ,  H01L27/32 ,  H01L33/52 ,  H01L27/13 ,  H01L51/52

CPC classification number: H01L27/1248 ,  G02F1/136227 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/1244 ,  H01L27/1255 ,  H01L27/13 ,  H01L27/3246 ,  H01L27/3276 ,  H01L33/52 ,  H01L51/5237 ,  H01L51/5253

Abstract: It is an object of the present invention to provide a semiconductor display device having an interlayer insulating film which can obtain planarity of a surface while controlling film formation time, can control treatment time of heating treatment with an object of removing moisture, and can prevent moisture in the interlayer insulating film from being discharged to a film or an electrode adjacent to the interlayer insulating film. An inorganic insulating film containing nitrogen, which is less likely to transmit moisture compared with an organic resin, is formed so as to cover a TFT. Next, an organic resin film containing photosensitive acrylic resin is applied to the organic insulting film, and the organic resin film is partially exposed to light to be opened. Thereafter, an inorganic insulting film containing nitrogen, which is less likely to transmit moisture compared with an organic resin, is formed so as to cover the opened organic resin film. Then, in the opening part of the organic resin film, a gate insulating film and the two layer inorganic insulating film containing nitrogen are opened partially by etching to expose an active layer of the TFT.

公开(公告)号：US09627010B2

公开(公告)日：2017-04-18

申请号：US14659914

申请日：2015-03-17

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takahiko Ishizu ,  Kiyoshi Kato ,  Tatsuya Onuki ,  Wataru Uesugi

IPC: G11C5/14 ,  G11C11/409 ,  G11C11/4074 ,  G11C11/419

CPC classification number: G11C5/147 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0685 ,  G11C11/419 ,  G11C14/0054

Abstract: Provided is a semiconductor device having a memory cell array, which is capable of existing in three power-gating states depending on a non-access period to the memory cell array. The memory cell array includes a plurality of memory cells which each have an SRAM and a nonvolatile memory portion having a transistor with an oxide semiconductor in a channel region. The three power-gating states includes: a first state in which a power-gating to the memory cell array is performed; a second state in which the power-gating is performed on the memory cell array and peripheral circuits which control the memory cell array; and a third state in which, in addition to the memory cell array and the peripheral circuits, a power supply voltage supplying circuit is subjected to the power gating.

公开(公告)号：US09589961B2

公开(公告)日：2017-03-07

申请号：US14678028

申请日：2015-04-03

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

IPC: G11C11/24 ,  H01L27/105 ,  G11C11/404 ,  G11C11/405 ,  G11C11/56 ,  H01L21/822 ,  H01L27/06 ,  H01L27/12 ,  H01L27/108 ,  H01L29/26 ,  G11C16/04 ,  G11C16/10 ,  H01L29/786 ,  H01L21/02 ,  H01L27/115

CPC classification number: H01L27/1052 ,  G11C5/06 ,  G11C7/12 ,  G11C11/404 ,  G11C11/405 ,  G11C11/565 ,  G11C16/0408 ,  G11C16/10 ,  G11C2211/4016 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1203 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/263 ,  H01L29/7869

Abstract: Disclosed is a semiconductor device functioning as a multivalued memory device including: memory cells connected in series; a driver circuit selecting a memory cell and driving a second signal line and a word line; a driver circuit selecting any of writing potentials and outputting it to a first signal line; a reading circuit comparing a potential of a bit line and a reference potential; and a potential generating circuit generating the writing potential and the reference potential. One of the memory cells includes: a first transistor connected to the bit line and a source line; a second transistor connected to the first and second signal line; and a third transistor connected to the word line, bit line, and source line. The second transistor includes an oxide semiconductor layer. A gate electrode of the first transistor is connected to one of source and drain electrodes of the second transistor.

Abstract translation: 公开了用作多值存储器件的半导体器件，包括：串联连接的存储器单元; 选择存储单元并驱动第二信号线和字线的驱动器电路; 选择写入电位的驱动器电路并将其输出到第一信号线; 读取电路，比较位线的电位和参考电位; 以及产生写入电位和参考电位的电位产生电路。 一个存储单元包括：连接到位线的第一晶体管和源极线; 连接到第一和第二信号线的第二晶体管; 以及连接到字线，位线和源极线的第三晶体管。 第二晶体管包括氧化物半导体层。 第一晶体管的栅电极连接到第二晶体管的源极和漏极之一。

公开(公告)号：US09525051B2

公开(公告)日：2016-12-20

申请号：US14740688

申请日：2015-06-16

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hiroki Inoue ,  Kiyoshi Kato ,  Takanori Matsuzaki ,  Shuhei Nagatsuka

IPC: G11C11/00 ,  H01L29/66 ,  G11C11/404 ,  G11C11/405 ,  G11C16/04 ,  H01L27/115 ,  H01L27/12 ,  H01L27/108 ,  G11C16/08 ,  G11C16/24 ,  H01L29/786 ,  H01L21/02 ,  H01L21/425 ,  H01L21/441 ,  H01L21/477 ,  G11C11/4091

CPC classification number: H01L27/1052 ,  G11C11/404 ,  G11C11/405 ,  G11C11/4091 ,  G11C16/0408 ,  G11C16/08 ,  G11C16/24 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/425 ,  H01L21/441 ,  H01L21/477 ,  H01L27/108 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/66969 ,  H01L29/78651 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device including a nonvolatile memory cell in which a writing transistor which includes an oxide semiconductor, a reading transistor which includes a semiconductor material different from that of the writing transistor, and a capacitor are included is provided. Data is written to the memory cell by turning on the writing transistor and applying a potential to a node where a source electrode (or a drain electrode) of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor, so that the predetermined amount of charge is held in the node. Further, when a p-channel transistor is used as the reading transistor, a reading potential is a positive potential.

公开(公告)号：US09472293B2

公开(公告)日：2016-10-18

申请号：US14990908

申请日：2016-01-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shuhei Nagatsuka ,  Hiroki Inoue ,  Takahiko Ishizu ,  Takanori Matsuzaki ,  Yutaka Shionoiri ,  Kiyoshi Kato

IPC: G11C16/08 ,  G11C16/24 ,  G11C16/04

CPC classification number: G11C16/24 ,  G11C11/5642 ,  G11C16/04 ,  G11C16/0408 ,  G11C16/0441 ,  G11C16/045 ,  G11C16/08 ,  H01L27/1156 ,  H01L27/1225 ,  H01L29/7869 ,  H01L29/78696

Abstract: To read multilevel data from a memory cell having a transistor using silicon and a transistor using an oxide semiconductor, without switching a signal for reading the multilevel data in accordance with the number of the levels of the multilevel data. The potential of the bit line is precharged, the electrical charge of the bit line is discharged via a transistor for writing data, and the potential of the bit line which is changed by the discharging is read as multilevel data. With such a structure, the potential corresponding to data held in a gate of the transistor can be read by only one-time switching of a signal for reading data.

公开(公告)号：US09461047B2

公开(公告)日：2016-10-04

申请号：US14548349

申请日：2014-11-20

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kiyoshi Kato

IPC: H01L27/12 ,  H01L27/108 ,  H01L29/786 ,  H01L27/06 ,  H01L27/105 ,  H01L27/115

CPC classification number: H01L27/108 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/7869

Abstract: Provided is a semiconductor device with a novel structure in which stored data can be retained even when power is not supplied, and which does not have a limitation on the number of writing. The semiconductor device includes both a memory circuit including a transistor including an oxide semiconductor (in a broader sense, a transistor whose off-state current is sufficiently small), and a peripheral circuit such as a driver circuit including a transistor including a material other than an oxide semiconductor (that is, a transistor capable of operating at sufficiently high speed). Further, the peripheral circuit is provided in a lower portion and the memory circuit is provided in an upper portion, so that the area and size of the semiconductor device can be decreased.

Abstract translation: 提供一种具有新颖结构的半导体器件，其中即使在未提供电力的情况下也可以保留存储的数据，并且对写入次数没有限制。 半导体器件包括包括氧化物半导体（在更广泛的意义上是截止电流足够小的晶体管）的晶体管的存储器电路和包括晶体管的诸如驱动器电路的外围电路，该晶体管包括除了 氧化物半导体（即，能够以足够高的速度运行的晶体管）。 此外，外围电路设置在下部，并且存储电路设置在上部，使得可以减小半导体器件的面积和尺寸。

公开(公告)号：US09412060B2

公开(公告)日：2016-08-09

申请号：US14500343

申请日：2014-09-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato ,  Takaaki Koen ,  Yuto Yakubo ,  Makoto Yanagisawa ,  Hisashi Ohtani ,  Eiji Sugiyama ,  Nozomi Horikoshi

IPC: H01L39/00 ,  G06K19/077 ,  H01L23/29 ,  H01L23/31

CPC classification number: G06K19/07735 ,  G06K19/07722 ,  G06K19/07794 ,  H01L23/295 ,  H01L23/3157 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00

Abstract: A semiconductor device capable of wireless communication, which has high reliability in terms of resistance to external force, in particular, pressing force and can prevent electrostatic discharge in an integrated circuit without preventing reception of an electric wave. The semiconductor device includes an on-chip antenna connected to the integrated circuit and a booster antenna which transmits a signal or power included in a received electric wave to the on-chip antenna without contact. In the semiconductor device, the integrated circuit and the on-chip antenna are interposed between a pair of structure bodies formed by impregnating a fiber body with a resin. One of the structure bodies is provided between the on-chip antenna and the booster antenna. A conductive film having a surface resistance value of approximately 106 to 1014 Ω/cm2 is formed on at least one surface of each structure body.

Abstract translation: 一种能够进行无线通信的半导体装置，其在外力方面具有高的可靠性，特别是按压力，并且能够防止集成电路中的静电放电，而不会妨碍电波的接收。 半导体器件包括连接到集成电路的片上天线和将接收到的电波中包含的信号或功率发送到片上天线而不接触的增强天线。 在半导体器件中，集成电路和片上天线插入通过用树脂浸渍纤维体而形成的一对结构体之间。 其中一个结构体设置在片上天线和增强天线之间。 在每个结构体的至少一个表面上形成表面电阻值为大约106至1014Ω/ cm2的导电膜。

公开(公告)号：US20160203871A1

公开(公告)日：2016-07-14

申请号：US14990908

申请日：2016-01-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shuhei Nagatsuka ,  Hiroki Inoue ,  Takahiko Ishizu ,  Takanori Matsuzaki ,  Yutaka Shionoiri ,  Kiyoshi Kato

IPC: G11C16/24

CPC classification number: G11C16/24 ,  G11C11/5642 ,  G11C16/04 ,  G11C16/0408 ,  G11C16/0441 ,  G11C16/045 ,  G11C16/08 ,  H01L27/1156 ,  H01L27/1225 ,  H01L29/7869 ,  H01L29/78696

Abstract: To read multilevel data from a memory cell having a transistor using silicon and a transistor using an oxide semiconductor, without switching a signal for reading the multilevel data in accordance with the number of the levels of the multilevel data. The potential of the bit line is precharged, the electrical charge of the bit line is discharged via a transistor for writing data, and the potential of the bit line which is changed by the discharging is read as multilevel data. With such a structure, the potential corresponding to data held in a gate of the transistor can be read by only one-time switching of a signal for reading data.

Abstract translation: 从具有使用硅的晶体管的存储单元和使用氧化物半导体的晶体管读取多电平数据，而不用根据多电平数据的电平数来切换用于读取多电平数据的信号。 位线的电位被预充电，位线的电荷通过用于写入数据的晶体管放电，并且由放电改变的位线的电位被读取为多电平数据。 通过这样的结构，可以通过仅读取数据的信号的一次切换来读取对应于保持在晶体管的栅极中的数据的电位。

公开(公告)号：US09196741B2

公开(公告)日：2015-11-24

申请号：US13751783

申请日：2013-01-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Kiyoshi Kato ,  Masakazu Murakami

IPC: H01L21/34 ,  H01L29/78 ,  H01L29/24 ,  H01L29/786

CPC classification number: H01L29/7869 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/45

Abstract: A semiconductor device with significantly low off-state current is provided. An oxide semiconductor material in which holes have a larger effective mass than electrons is used. A transistor is provided which includes a gate electrode layer, a gate insulating layer, an oxide semiconductor layer including a hole whose effective mass is 5 or more times, preferably 10 or more times, further preferably 20 or more times that of an electron in the oxide semiconductor layer, a source electrode layer in contact with the oxide semiconductor layer, and a drain electrode layer in contact with the oxide semiconductor layer.

Abstract translation: 提供具有非常低的截止电流的半导体器件。 使用空穴具有比电子更大的有效质量的氧化物半导体材料。 提供了一种晶体管，其包括栅极电极层，栅极绝缘层，氧化物半导体层，其有效质量为有效质量的5倍以上，优选为10倍以上，更优选为20倍以上 氧化物半导体层，与氧化物半导体层接触的源电极层以及与氧化物半导体层接触的漏电极层。