公开(公告)号：US20050112858A1

公开(公告)日：2005-05-26

申请号：US10717582

申请日：2003-11-21

申请人： Han-Ming Yuan ,  Yi-Nan Chen

发明人： Han-Ming Yuan ,  Yi-Nan Chen

IPC分类号： H01L21/44 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242

CPC分类号： H01L21/76897 ,  H01L21/76802 ,  H01L27/10888 ,  H01L27/10894

摘要： Disclosed is a contact hole forming method for forming gate contact holes and non-gate contact holes. The method of this invention comprises the steps of providing a substrate; forming a plurality of operation layers on the substrate as required, wherein the operation layers of the gate contact hole forming portion comprise at least a gate metal and a cap nitride layer on the gate metal; forming an additional nitride layer on the uppermost layer of the operation layers; forming photoresist on the additional nitride layer to define the positions of the respective contact holes to be formed; forming the non-gate contact hole and removing the portion of the operation layers corresponding to the gate contact hole forming position above the cap nitride by etching; filling the non-gate contact hole with photoresist; and forming the gate contact hole through removing the cap nitride portion corresponding to the gate contact hole forming position and removing all the additional nitride layer by etching.

摘要翻译： 公开了一种用于形成栅极接触孔和非栅极接触孔的接触孔形成方法。 本发明的方法包括提供基底的步骤; 根据需要在所述基板上形成多个操作层，其中所述栅极接触孔形成部分的操作层至少在所述栅极金属上至少包括栅极金属和帽状氮化物层; 在操作层的最上层形成附加的氮化物层; 在另外的氮化物层上形成光致抗蚀剂以限定待形成的各个接触孔的位置; 形成非栅极接触孔，并且通过蚀刻去除与顶盖氮化物上方的栅极接触孔形成位置相对应的操作层的部分; 用光刻胶填充非栅极接触孔; 以及通过移除对应于栅极接触孔形成位置的顶部氮化物部分并通过蚀刻去除所有附加氮化物层来形成栅极接触孔。

公开(公告)号：US20050090064A1

公开(公告)日：2005-04-28

申请号：US10998219

申请日：2004-11-26

申请人： Ming-Cheng Chang ,  Yi-Chen Chen ,  Yi-Nan Chen

发明人： Ming-Cheng Chang ,  Yi-Chen Chen ,  Yi-Nan Chen

IPC分类号： H01L21/20 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/10 ,  H01L29/76 ,  H01L29/78 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L21/26586 ,  H01L27/10832 ,  H01L27/10838 ,  H01L27/10864 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/1037 ,  H01L29/78 ,  H01L29/945

摘要： A partial vertical memory cell and fabrication method thereof. A semiconductor substrate is provided, in which two deep trenches having deep trench capacitors respectively are formed, and the deep trench capacitors are lower than a top surface of the semiconductor substrate. A portion of the semiconductor outside the deep trenches is removed to form a pillar between. The pillar is ion implanted to form an ion-doped area in the pillar corner acting as a S/D area. A gate dielectric layer and a conducting layer are conformally formed on the pillar sequentially. An isolation is formed in the semiconductor substrate beside the conducting layer. The conducting layer is defined to form a first gate and a second gate.

公开(公告)号：US20050079649A1

公开(公告)日：2005-04-14

申请号：US10709054

申请日：2004-04-09

申请人： Shao-Kang Chang ,  Graham Chuang ,  Yi-Nan Chen

发明人： Shao-Kang Chang ,  Graham Chuang ,  Yi-Nan Chen

IPC分类号： C09K13/04 ,  C09K13/08 ,  G01N1/32 ,  H01L21/00 ,  H01L21/66

CPC分类号： C09K13/08 ,  G01N1/32 ,  H01J2237/28

摘要： An etchant composition for SEM image enhancement of P-N junction contrast. The composition comprises an NTC-1 solution mixed with an NTC-2 solution at a specific volumetric ratio. The NTC-1 solution is prepared by mixing solution “A” comprising organic acid, HF, and nitric acid with a 49% HF solution. The NTC-2 solution comprises metal ions and a strong oxidant. After the preparation of the NTC-1 and NTC-2 solutions, they are mixed together at specific volumetric ratio. Before carrying out an SEM analysis, the SEM specimen is dipped into the etchant composition.

摘要翻译： 用于P-N结对比度的SEM图像增强的蚀刻剂组合物。 该组合物包含以特定体积比与NTC-2溶液混合的NTC-1溶液。 通过将包含有机酸HF和硝酸的溶液“A”与49％HF溶液混合来制备NTC-1溶液。 NTC-2溶液包含金属离子和强氧化剂。 在制备NTC-1和NTC-2溶液后，将它们以特定的体积比混合在一起。 在进行SEM分析之前，将SEM样品浸入蚀刻剂组合物中。

公开(公告)号：US06872629B2

公开(公告)日：2005-03-29

申请号：US10722647

申请日：2003-11-26

申请人： Chih-Yuan Hsiao ,  Yi-Nan Chen

发明人： Chih-Yuan Hsiao ,  Yi-Nan Chen

IPC分类号： H01L21/20 ,  H01L21/8242

CPC分类号： H01L27/10867 ,  H01L27/10864

摘要： A method of forming a memory cell with a single sided buried strap. A collar oxide layer is formed on the sidewall of a trench. A conductive layer fills the trench. The conductive layer and the collar oxide layer are partially removed to form an opening having first and second sidewalls. The remaining collar oxide layer is lower than the remaining conductive layer. An angle implantation with F ions is performed on the first sidewall. A thermal oxidation process is performed to form a first oxide layer on the first sidewall and a second oxide layer on the second sidewall. The first oxide layer is thicker than the second oxide layer. The second oxide layer is removed to expose the second sidewall. A buried strap is formed at the bottom of the opening, insulated from the first sidewall by the first oxide layer.

摘要翻译： 一种用单面埋置带形成存储单元的方法。 环状氧化物层形成在沟槽的侧壁上。 导电层填充沟槽。 导电层和套环氧化物层被部分去除以形成具有第一和第二侧壁的开口。 剩余的环状氧化物层比剩余的导电层低。 在第一侧壁上进行具有F离子的角度注入。 进行热氧化处理以在第一侧壁上形成第一氧化物层，在第二侧壁上形成第二氧化物层。 第一氧化物层比第二氧化物层厚。 去除第二氧化物层以暴露第二侧壁。 在开口的底部形成掩埋带，通过第一氧化物层与第一侧壁绝缘。

公开(公告)号：US06872619B2

公开(公告)日：2005-03-29

申请号：US10620869

申请日：2003-07-16

申请人： Yi-Nan Chen ,  Tieh-Chiang Wu ,  Feng-Chuan Lin

发明人： Yi-Nan Chen ,  Tieh-Chiang Wu ,  Feng-Chuan Lin

IPC分类号： H01L21/76 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10864 ,  H01L27/10867

摘要： A method for forming a semiconductor device having a trench top isolation layer. A collar insulating layer is formed over a lower portion of the sidewall of the trench formed in a substrate. A first conductive layer is formed in the lower portion of the trench and protrudes the collar insulating layer, and a second conductive layer is formed overlying the first conductive layer and covers the collar insulating layer. An insulating spacer is formed over an upper portion of the sidewall of the trench and separated from the second conductive layer by a gap. The second conductive layer is partially thermally oxidized to form an oxide layer thereon whereby the gap is filled. After the oxide layer is removed, a reverse T-shaped insulating layer is formed thereon by chemical vapor deposition to serve as a trench top isolation layer. Finally, the insulating spacer is removed.

摘要翻译： 一种形成具有沟槽顶部隔离层的半导体器件的方法。 环形绝缘层形成在形成在衬底中的沟槽的侧壁的下部上。 第一导电层形成在沟槽的下部并突出轴环绝缘层，并且形成第二导电层，覆盖第一导电层并覆盖轴环绝缘层。 在沟槽的侧壁的上部形成绝缘间隔物，并与第二导电层隔开间隙。 第二导电层被部分地热氧化以在其上形成氧化物层，由此填充间隙。 在去除氧化物层之后，通过化学气相沉积在其上形成反向T形绝缘层，以用作沟槽顶部隔离层。 最后，去除绝缘垫片。

公开(公告)号：US06867142B2

公开(公告)日：2005-03-15

申请号：US10247422

申请日：2002-09-18

申请人： Yi-Nan Chen ,  Shing-Yih Shih ,  Hsien-Wen Liu

发明人： Yi-Nan Chen ,  Shing-Yih Shih ,  Hsien-Wen Liu

IPC分类号： H01L21/321 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/302 ,  C09K13/00

CPC分类号： H01L21/32134 ,  H01L21/3212 ,  H01L21/76877

摘要： A method to prevent electrical shorts between tungsten interconnects. First, a semiconductor substrate having an insulating layer thereon is provided. Then, the insulating layer is selectively etched to form a trench for interconnect. Then, a titanium nitride film is conformally deposited on the surface of the trench and the insulating layer. A tungsten layer is then deposited to fill the trench. Next, the tungsten layer above the titanium nitride film is removed by an ammonia hydrogen peroxide mixture (APM) solution. Next, the titanium nitride film above the insulating layer is removed by a sulfuric acid hydrogen peroxide mixture (SPM) solution to leave a tungsten interconnect within the trench.

摘要翻译： 防止钨互连之间电短路的方法。 首先，提供其上具有绝缘层的半导体衬底。 然后，选择性地蚀刻绝缘层以形成用于互连的沟槽。 然后，氮化钛膜被共形沉积在沟槽和绝缘层的表面上。 然后沉积钨层以填充沟槽。 接下来，通过氨过氧化氢混合物（APM）溶液除去氮化钛膜上方的钨层。 接下来，通过硫酸过氧化氢混合物（SPM）溶液除去绝缘层上方的氮化钛膜，以在沟槽内留下钨互连。

公开(公告)号：US20050051191A1

公开(公告)日：2005-03-10

申请号：US10707081

申请日：2003-11-20

申请人： Shih-Chieh Kao ,  Jin-Tau Huang ,  Yi-Nan Chen

发明人： Shih-Chieh Kao ,  Jin-Tau Huang ,  Yi-Nan Chen

IPC分类号： B08B11/00 ,  H01L21/306 ,  H01L21/311 ,  H01L21/768

CPC分类号： H01L21/02063 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76838

摘要： A cleaning method used in the fabrication of metallic interconnects is provided. A substrate having a conductive layer and a dielectric layer on the conductive layer is provided. An opening is formed in the dielectric layer. The opening exposes a portion of the conductive layer. The opening is cleaned using a mixture containing sulfuric acid and hydrogen peroxide. In this invention, the mixture containing sulfuric acid and hydrogen peroxide provides an effective means of removing the residues within the opening so that the electrical conductivity of a subsequently formed contact is improved.

摘要翻译： 提供了用于制造金属互连件的清洁方法。 提供了在导电层上具有导电层和电介质层的衬底。 在电介质层中形成开口。 开口暴露导电层的一部分。 使用含有硫酸和过氧化氢的混合物清洁开口。 在本发明中，含有硫酸和过氧化氢的混合物提供了去除开口内残留物的有效手段，从而提高随后形成的触点的导电性。

公开(公告)号：US20050048766A1

公开(公告)日：2005-03-03

申请号：US10605007

申请日：2003-08-31

申请人： Wen-Chieh Wu ,  Yi-Nan Chen ,  Chun-Yi Wu

发明人： Wen-Chieh Wu ,  Yi-Nan Chen ,  Chun-Yi Wu

IPC分类号： H01L21/285 ,  H01L21/768 ,  H01L21/4763 ,  H01L21/22 ,  H01L21/38 ,  H01L21/44

CPC分类号： H01L21/76877 ,  H01L21/28525

摘要： A method for fabricating a conductive plug device is disclosed. A semiconductor substrate having a diffusion region thereon is provided. A dielectric layer is deposited over the semiconductor substrate. An opening is formed in the dielectric layer to expose a portion of the diffusion region. An un-doped CVD silicon layer is deposited on interior walls of the opening. A pure CVD phosphorus layer is in-situ deposited on the un-doped CVD silicon layer. The pure CVD phosphorus layer thereafter diffuses into the subjacent un-doped CVD silicon layer to form a doped silicon layer. Subsequently, a second un-doped CVD silicon layer is in-situ deposited on the doped silicon layer.

摘要翻译： 公开了一种制造导电塞装置的方法。 提供其上具有扩散区域的半导体衬底。 介电层沉积在半导体衬底上。 在电介质层中形成开口以暴露扩散区的一部分。 未掺杂的CVD硅层沉积在开口的内壁上。 在未掺杂的CVD硅层上原位沉积纯的CVD磷层。 然后，纯的CVD磷层扩散到下面的未掺杂的CVD硅层中以形成掺杂的硅层。 随后，第二未掺杂的CVD硅层原位沉积在掺杂的硅层上。

公开(公告)号：US20050048763A1

公开(公告)日：2005-03-03

申请号：US10727966

申请日：2003-12-04

申请人： Kaan-Lu Tzou ,  Yan-Hong Chen ,  Yi-Nan Chen ,  Chang-Rong Wu

发明人： Kaan-Lu Tzou ,  Yan-Hong Chen ,  Yi-Nan Chen ,  Chang-Rong Wu

IPC分类号： H01L21/3105 ,  H01L21/316 ,  H01L21/768 ,  H01L21/4763 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/02129 ,  H01L21/0234 ,  H01L21/02362 ,  H01L21/3105 ,  H01L21/31612 ,  H01L21/31625 ,  H01L21/76802 ,  H01L21/76819 ,  H01L21/76826 ,  H01L21/76829

摘要： A method of forming an interlayer dielectric (ILD) layer. A dielectric layer containing boron and phosphorous is formed overlying a substrate. A plasma treatment is subsequently performed on the dielectric layer using argon or nitrogen as a process gas. A capping layer is formed in-situ overlying the dielectric layer to serve as the ILD layer with the dielectric layer. A reflow process is subsequently performed on the ILD layer. A method for preventing formation of etching defects in a contact is also disclosed.

公开(公告)号：US20050032359A1

公开(公告)日：2005-02-10

申请号：US10715658

申请日：2003-11-18

申请人： Chung-Peng Hao ,  Yi-Nan Chen

发明人： Chung-Peng Hao ,  Yi-Nan Chen

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/4763 ,  H01L29/78

CPC分类号： H01L29/66553 ,  H01L21/28052 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/6659 ,  H01L29/7833

摘要： The invention provides a damascene gate process. A semiconductor substrate having a pad layer and an etch stop layer formed thereon is provided, and an insulating layer is formed to cover the etch stop layer, followed by forming an opening by partially removing the insulating layer, the etch stop layer, and the pad layer. A protective spacer is formed on the sidewall of the opening, wherein the top of the protective spacer is lower than the insulating layer. A gate conducting layer is then formed in the opening. The protective spacer and the insulating layer are removed to expose a portion of the semiconductor substrate and the etch stop layer. Implantation is then performed to form lightly doped drains. Agate spacer is then formed to cover the gate conducting layer. The etch stop layer and the pad layer are removed, and implantation is then performed to a form source/drain.

摘要翻译： 本发明提供一种镶嵌门工艺。 提供具有形成在其上的焊盘层和蚀刻停止层的半导体衬底，并且形成绝缘层以覆盖蚀刻停止层，随后通过部分去除绝缘层，蚀刻停止层和焊盘形成开口 层。 保护间隔件形成在开口的侧壁上，其中保护间隔物的顶部低于绝缘层。 然后在开口中形成栅极导电层。 去除保护间隔物和绝缘层以暴露半导体衬底和蚀刻停止层的一部分。 然后进行植入以形成轻掺杂的排水沟。 然后形成玛瑙垫片以覆盖栅极导电层。 去除蚀刻停止层和焊盘层，然后对形式源/漏极进行注入。