公开(公告)号：US09755964B2

公开(公告)日：2017-09-05

申请号：US14859844

申请日：2015-09-21

Applicant: Advanced Micro Devices, Inc.

Inventor： David A. Roberts ,  Michael Ignatowski ,  Nuwan Jayasena ,  Gabriel H. Loh

IPC: H04L12/40 ,  H04L12/781 ,  H04L29/06 ,  H04L12/715 ,  H04L12/861

CPC classification number: H04L45/52 ,  H04L45/04 ,  H04L49/9057 ,  H04L69/08

Abstract: A communication device includes a data source that generates data for transmission over a bus, and a data encoder that receives and encodes outgoing data. An encoder system receives outgoing data from a data source and stores the outgoing data in a first queue. An encoder encodes outgoing data with a header type that is based upon a header type indication from a controller and stores the encoded data that may be a packet or a data word with at least one layered header in a second queue for transmission. The device is configured to receive at a payload extractor, a packet protocol change command from the controller and to remove the encoded data and to re-encode the data to create a re-encoded data packet and placing the re-encoded data packet in the second queue for transmission.

公开(公告)号：US09727241B2

公开(公告)日：2017-08-08

申请号：US14616058

申请日：2015-02-06

Applicant: Advanced Micro Devices, Inc.

Inventor： Gabriel H. Loh ,  David A. Roberts ,  Mitesh R. Meswani ,  Mark R. Nutter ,  John R. Slice ,  Prashant Nair ,  Michael Ignatowski

IPC: G06F12/10 ,  G06F3/06 ,  G06F12/0893 ,  G06F12/1045

CPC classification number: G06F3/0604 ,  G06F3/0653 ,  G06F3/0673 ,  G06F12/0893 ,  G06F12/1027 ,  G06F12/1045 ,  G06F2212/60 ,  G06F2212/68

Abstract: A processor maintains a count of accesses to each memory page. When the accesses to a memory page exceed a threshold amount for that memory page, the processor sets an indicator for the page. Based on the indicators for the memory pages, the processor manages data at one or more levels of the processor's memory hierarchy.

公开(公告)号：US09552294B2

公开(公告)日：2017-01-24

申请号：US13736063

申请日：2013-01-07

Applicant: Advanced Micro Devices, Inc.

Inventor： Jaewoong Sim ,  Mithuna S. Thottethodi ,  Gabriel H. Loh

IPC: G06F12/00 ,  G06F12/08

CPC classification number: G06F12/0802 ,  G06F12/0804 ,  G06F12/0862 ,  G06F12/0888

Abstract: The described embodiments include a main memory and a cache memory (or “cache”) with a cache controller that includes a mode-setting mechanism. In some embodiments, the mode-setting mechanism is configured to dynamically determine an access pattern for the main memory. Based on the determined access pattern, the mode-setting mechanism configures at least one region of the main memory in a write-back mode and configures other regions of the main memory in a write-through mode. In these embodiments, when performing a write operation in the cache memory, the cache controller determines whether a region in the main memory where the cache block is from is configured in the write-back mode or the write-through mode and then performs a corresponding write operation in the cache memory.

Abstract translation: 所描述的实施例包括具有包括模式设置机制的高速缓存控制器的主存储器和高速缓冲存储器（或“高速缓存”）。 在一些实施例中，模式设置机制被配置为动态地确定主存储器的访问模式。 基于确定的访问模式，模式设置机制以回写模式配置主存储器的至少一个区域，并以直通模式配置主存储器的其他区域。 在这些实施例中，当在高速缓冲存储器中执行写入操作时，高速缓存控制器确定高速缓存块所处的主存储器中的区域是否配置在回写模式或直写模式中，然后执行相应的 在高速缓存中写入操作。

公开(公告)号：US09405703B2

公开(公告)日：2016-08-02

申请号：US14296361

申请日：2014-06-04

Applicant: Advanced Micro Devices, Inc.

Inventor： Gabriel H. Loh

IPC: G06F12/10

CPC classification number: G06F12/1054 ,  G06F12/1027 ,  G06F2212/608 ,  G06F2212/68 ,  Y02D10/13

Abstract: The described embodiments include a translation lookaside buffer (“TLB”) that is used for performing virtual address to physical address translations when making memory accesses in a memory in a computing device. In the described embodiments, the TLB includes a hierarchy of tables that are each used for performing virtual address to physical address translations based on the arrangement of pages of memory in corresponding regions of the memory. When performing a virtual address to physical address translation, the described embodiments perform a lookup in each of the tables in parallel for the virtual address to physical address translation and use a physical address that is returned from a lowest table in the hierarchy as the translation.

Abstract translation: 所描述的实施例包括在计算设备中的存储器中进行存储器访问时用于执行虚拟地址到物理地址转换的翻译后备缓冲器（“TLB”）。 在所描述的实施例中，TLB包括基于存储器的相应区域中的存储器页面的布置而各自用于执行虚拟地址到物理地址转换的表的层级。 当对物理地址转换执行虚拟地址时，所描述的实施例在虚拟地址到物理地址转换中并行地对每个表执行查找，并且使用从层级中的最低表返回的物理地址作为翻译。

公开(公告)号：US20160179382A1

公开(公告)日：2016-06-23

申请号：US14576912

申请日：2014-12-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Sergey Blagodurov ,  Mitesh Ramesh Meswani ,  Gabriel H. Loh ,  Mauricio Breternitz, JR. ,  Mark Richard Nutter ,  John Robert Slice ,  David Andrew Roberts ,  Michael Ignatowski ,  Mark Henry Oskin

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/061 ,  G06F3/0634 ,  G06F3/0673 ,  G06F3/0685

Abstract: A processor modifies memory management mode for a range of memory locations of a multilevel memory hierarchy based on changes in an application phase of an application executing at a processor. The processor monitors the application phase (e.g.,. computation-bound phase, input/output phase, or memory access phase) of the executing application and in response to a change in phase consults a management policy to identify a memory management mode. The processor automatically reconfigures a memory controller and other modules so that a range of memory locations of the multilevel memory hierarchy are managed according to the identified memory management mode. By changing the memory management mode for the range of memory locations according to the application phase, the processor improves processing efficiency and flexibility.

Abstract translation: 处理器基于在处理器上执行的应用的应用阶段的变化来修改多层存储器层级的一系列存储器位置的存储器管理模式。 处理器监视执行应用程序的应用阶段（例如，计算限制阶段，输入/输出阶段或存储器访问阶段）并且响应于阶段的改变来咨询管理策略以识别存储器管理模式。 处理器自动重新配置存储器控制器和其他模块，使得根据所识别的存储器管理模式来管理多级存储器层级的一系列存储器位置。 通过根据应用阶段改变存储器位置范围的存储器管理模式，处理器提高了处理效率和灵活性。

公开(公告)号：US09251081B2

公开(公告)日：2016-02-02

申请号：US13957105

申请日：2013-08-01

Applicant: Advanced Micro Devices, Inc.

Inventor： Kai K. Chang ,  Yasuko Eckert ,  Gabriel H. Loh ,  Lisa R. Hsu

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0848 ,  G06F12/122 ,  Y02D10/13

Abstract: A system and method for efficiently powering down banks in a cache memory for reducing power consumption. A computing system includes a cache array and a corresponding cache controller. The cache array includes multiple banks, each comprising multiple cache sets. In response to a request to power down a first bank of the multiple banks in the cache array, the cache controller selects a cache line of a given type in the first bank and determines whether a respective locality of reference for the selected cache line exceeds a threshold. If the threshold is exceeded, then the selected cache line is migrated to a second bank in the cache array. If the threshold is not exceeded, then the selected cache line is written back to lower-level memory.

公开(公告)号：US09251069B2

公开(公告)日：2016-02-02

申请号：US14055869

申请日：2013-10-16

Applicant: Advanced Micro Devices, Inc.

Inventor： Yasuko Eckert ,  Gabriel H. Loh ,  Mauricio Breternitz ,  James M. O'Connor ,  Srilatha Manne ,  Nuwan S. Jayasena ,  Mithuna S. Thottethodi

IPC: G06F12/08

CPC classification number: G06F12/0808 ,  G06F1/3225 ,  G06F1/3275 ,  G06F12/0848 ,  G06F12/0888 ,  G06F12/0897 ,  Y02D10/13 ,  Y02D10/14

Abstract: A system and method for efficiently limiting storage space for data with particular properties in a cache memory. A computing system includes a cache array and a corresponding cache controller. The cache array includes multiple banks, wherein a first bank is powered down. In response a write request to a second bank for data indicated to be stored in the powered down first bank, the cache controller determines a respective bypass condition for the data. If the bypass condition exceeds a threshold, then the cache controller invalidates any copy of the data stored in the second bank. If the bypass condition does not exceed the threshold, then the cache controller stores the data with a clean state in the second bank. The cache controller writes the data in a lower-level memory for both cases.

Abstract translation: 一种用于有效地限制高速缓冲存储器中具有特定属性的数据的存储空间的系统和方法。 计算系统包括高速缓存阵列和对应的高速缓存控制器。 高速缓存阵列包括多个存储体，其中第一存储体断电。 作为响应，向第二存储体写入请求以指示存储在掉电第一存储体中的数据，高速缓存控制器确定数据的相应旁路条件。 如果旁路条件超过阈值，则高速缓存控制器使存储在第二组中的数据的任何副本无效。 如果旁路条件不超过阈值，则高速缓存控制器将具有干净状态的数据存储在第二存储体中。 高速缓存控制器将这些数据写入较低级别的内存。

公开(公告)号：US09065722B2

公开(公告)日：2015-06-23

申请号：US13726142

申请日：2012-12-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Mithuna S. Thottethodi ,  Gabriel H. Loh

IPC: G06F17/50 ,  H04L12/755 ,  H01L23/48 ,  H01L23/538 ,  H01L25/065 ,  H04L12/701 ,  H01L25/18

CPC classification number: H04L45/021 ,  G06F17/5068 ,  H01L23/481 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2924/1461 ,  H01L2924/15192 ,  H04L45/00 ,  H01L2924/00

Abstract: An electronic assembly includes horizontally-stacked die disposed at an interposer, and may also include vertically-stacked die. The stacked die are interconnected via a multi-hop communication network that is partitioned into a link partition and a router partition. The link partition is at least partially implemented in the metal layers of the interposer for horizontally-stacked die. The link partition may also be implemented in part by the intra-die interconnects in a single die and by the inter-die interconnects connecting vertically-stacked sets of die. The router partition is implemented at some or all of the die disposed at the interposer and comprises the logic that supports the functions that route packets among the components of the processing system via the interconnects of the link partition. The router partition may implement fixed routing, or alternatively may be configurable using programmable routing tables or configurable logic blocks.

Abstract translation: 电子组件包括设置在插入器处的水平堆叠的管芯，并且还可以包括垂直堆叠的管芯。 堆叠的管芯通过被划分成链路分区和路由器分区的多跳通信网络相互连接。 连接分隔件至少部分地实现在用于水平堆叠的模具的插入件的金属层中。 链路分区还可以部分地由单个管芯中的管芯内互连和通过垂直堆叠的管芯组连接的晶片间互连来实现。 路由器分区在设置在插入器处的部分或全部芯片上实现，并且包括支持通过链路分区的互连来在处理系统的组件之间路由分组的功能的逻辑。 路由器分区可以实现固定路由，或者可以使用可编程路由表或可配置逻辑块来配置。

公开(公告)号：US08922243B2

公开(公告)日：2014-12-30

申请号：US13726145

申请日：2012-12-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Nuwan S. Jayasena ,  Michael J. Schulte ,  Gabriel H. Loh ,  Michael Ignatowski

IPC: H03K19/177 ,  G11C7/00

CPC classification number: H03K19/1776 ,  G06F11/1004 ,  G06F13/1668 ,  G06F13/4234 ,  G06F15/7867 ,  G11C7/1006 ,  G11C7/1048 ,  G11C29/70 ,  H01L2224/16227 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H03K19/17776 ,  Y02D10/14 ,  Y02D10/151

Abstract: A die-stacked memory device incorporates a reconfigurable logic device to provide implementation flexibility in performing various data manipulation operations and other memory operations that use data stored in the die-stacked memory device or that result in data that is to be stored in the die-stacked memory device. One or more configuration files representing corresponding logic configurations for the reconfigurable logic device can be stored in a configuration store at the die-stacked memory device, and a configuration controller can program a reconfigurable logic fabric of the reconfigurable logic device using a selected one of the configuration files. Due to the integration of the logic dies and the memory dies, the reconfigurable logic device can perform various data manipulation operations with higher bandwidth and lower latency and power consumption compared to devices external to the die-stacked memory device.

Abstract translation: 芯片堆叠的存储器件包括可重构逻辑器件，以在执行各种数据操作操作和使用存储在管芯堆叠的存储器件中的数据的其他存储器操作中提供实现灵活性，或者导致要存储在管芯堆叠存储器件中的数据。 堆叠式存储设备。 代表可重配置逻辑器件的相应逻辑配置的一个或多个配置文件可被存储在管芯堆叠的存储器件的配置存储器中，并且配置控制器可使用所选择的一个存储器件对可重新配置的逻辑器件进行编程 配置文件。 由于逻辑管芯和存储器管芯的集成，与可堆叠存储器件外部的器件相比，可重构逻辑器件可以执行具有更高带宽和更低延迟和功耗的各种数据操作操作。

公开(公告)号：US20140376320A1

公开(公告)日：2014-12-25

申请号：US13926155

申请日：2013-06-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Gabriel H. Loh ,  Vilas Sridharan ,  James M. O'Connor

IPC: G11C29/04

CPC classification number: G11C29/76 ,  G11C11/401

Abstract: A memory subsystem employs spare memory cells external to one or more memory devices. In some embodiments, a processing system uses the spare memory cells to replace individual selected cells at the protected memory, whereby the selected cells are replaced on a cell-by-cell basis, rather than exclusively on a row-by-row, column-by-column, or block-by-block basis. This allows faulty memory cells to be replaced efficiently, thereby improving memory reliability and manufacturing yields, without requiring large blocks of spare memory cells.

Abstract translation: 存储器子系统在一个或多个存储器件外部使用备用存储器单元。 在一些实施例中，处理系统使用备用存储器单元来替换受保护存储器处的各个所选择的单元，由此所选择的单元在逐个单元的基础上被替代，而不是仅排列在逐列的列上， 逐列或逐块的基础。 这样可以有效地更换故障存储单元，从而提高存储器的可靠性和制造成本，而不需要大量的备用存储单元。