公开(公告)号：US20140051223A1

公开(公告)日：2014-02-20

申请号：US14064787

申请日：2013-10-28

Applicant: Intermolecular Inc. ,  SanDisk 3D LLC ,  Kabushiki Kaisha Toshiba

Inventor： Dipankar Pramanik ,  Tony P. Chiang ,  Mankoo Lee

IPC: H01L45/00

CPC classification number: H01L45/14 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0045 ,  G11C2013/0073 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/76 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/10 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16

Abstract: A resistor structure incorporated into a resistive switching memory cell or device to form memory devices with improved device performance and lifetime is provided. The resistor structure may be a two-terminal structure designed to reduce the maximum current flowing through a memory device. A method is also provided for making such memory device. The method includes depositing a resistor structure and depositing a variable resistance layer of a resistive switching memory cell of the memory device, where the resistor structure is disposed in series with the variable resistance layer to limit the switching current of the memory device. The incorporation of the resistor structure is very useful in obtaining desirable levels of device switching currents that meet the switching specification of various types of memory devices. The memory devices may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices.

公开(公告)号：US20140051210A1

公开(公告)日：2014-02-20

申请号：US14062473

申请日：2013-10-24

Applicant: Intermolecular Inc.

Inventor： Sandra G Malhotra ,  Sean Barstow ,  Tony P. Chiang ,  Pragati KUMAR ,  Prashant B Phatak ,  Sunil Shanker ,  Wen Wu

IPC: H01L45/00

CPC classification number: H01L45/1608 ,  H01L27/2418 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1641

Abstract: Nonvolatile memory elements that are based on resistive switching memory element layers are provided. A nonvolatile memory element may have a resistive switching metal oxide layer. The resistive switching metal oxide layer may have one or more layers of oxide. A resistive switching metal oxide may be doped with a dopant that increases its melting temperature and enhances its thermal stability. Layers may be formed to enhance the thermal stability of the nonvolatile memory element. An electrode for a nonvolatile memory element may contain a conductive layer and a buffer layer.

公开(公告)号：US20140038352A1

公开(公告)日：2014-02-06

申请号：US14046029

申请日：2013-10-04

Applicant: Intermolecular Inc.

Inventor： Prashant B Phatak ,  Tony P. Chiang ,  Pragati KUMAR ,  Michael Miller

IPC: H01L45/00

CPC classification number: H01L45/146 ,  G11C13/0007 ,  G11C2213/32 ,  G11C2213/55 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2463 ,  H01L29/8615 ,  H01L45/08 ,  H01L45/10 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/165 ,  H01L45/1658 ,  H01L47/00

Abstract: Non-volatile resistive-switching memories are described, including a memory element having a first electrode, a second electrode, a metal oxide between the first electrode and the second electrode. The metal oxide switches using bulk-mediated switching, has a bandgap greater than 4 electron volts (eV), has a set voltage for a set operation of at least one volt per one hundred angstroms of a thickness of the metal oxide, and has a leakage current density less than 40 amps per square centimeter (A/cm2) measured at 0.5 volts (V) per twenty angstroms of the thickness of the metal oxide.

Abstract translation: 描述了非易失性电阻式切换存储器，包括在第一电极和第二电极之间具有第一电极，第二电极，金属氧化物的存储元件。 使用大容量介导的开关的金属氧化物开关具有大于4电子伏特（eV）的带隙，具有用于金属氧化物的厚度每100埃至少一伏特的设定操作的设定电压，并且具有 漏电流密度小于每平方厘米40安培（A / cm2），每0.5伏（V），金属氧化物厚度每20埃测得。

公开(公告)号：US20130314974A1

公开(公告)日：2013-11-28

申请号：US13957324

申请日：2013-08-01

Applicant: Intermolecular, Inc.

Inventor： Yun Wang ,  Tony P. Chiang ,  Prashant B. Phatak

IPC: G11C13/00

CPC classification number: G11C13/02 ,  G11C7/00 ,  G11C11/36 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0021 ,  G11C13/0069 ,  G11C13/04 ,  G11C2013/0073 ,  G11C2013/0092 ,  G11C2213/72

Abstract: According to various embodiments, a resistive-switching memory element and memory element array that uses a bipolar switching includes a select element comprising only a single diode that is not a Zener diode. The resistive-switching memory elements described herein can switch even when a switching voltage less than the breakdown voltage of the diode is applied in the reverse-bias direction of the diode. The memory elements are able to switch during the very brief period when a transient pulse voltage is visible to the memory element, and therefore can use a single diode per memory cell.

公开(公告)号：US08575021B2

公开(公告)日：2013-11-05

申请号：US13829290

申请日：2013-03-14

Applicant: Intermolecular, Inc.

Inventor： Thomas R. Boussie ,  Tony P. Chiang ,  Anh Duong ,  Zachary Fresco ,  Nitin Kumar ,  Chi-I Lang ,  Sandra G. Malhotra ,  Jinhong Tong

IPC: H01L21/31 ,  H01L21/312 ,  H01L21/32

CPC classification number: H01L21/02112 ,  H01L21/02123 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/76834 ,  H01L21/7685

Abstract: Methods for substrate processing are described. The methods include forming a material layer on a substrate. The methods include selecting constituents of a molecular masking layer (MML) to remove an effect of variations in the material layer as a result of substrate processing. The methods include normalizing the surface characteristics of the material layer by selectively depositing the MML on the material layer.

Abstract translation: 描述基板处理方法。 所述方法包括在基底上形成材料层。 所述方法包括选择分子屏蔽层（MML）的成分以消除作为衬底处理的结果的材料层中的变化的影响。 所述方法包括通过在材料层上选择性地沉积MML来使材料层的表面特性归一化。

公开(公告)号：US20130214238A1

公开(公告)日：2013-08-22

申请号：US13804318

申请日：2013-03-14

Applicant: INTERMOLECULAR INC. ,  KABUSHIKI KAISHA TOSHIBA ,  SANDISK 3D LLC

Inventor： Dipankar Pramanik ,  Tony P. Chiang ,  Tim Minvielle ,  Takeshi Yamaguchi

IPC: H01L45/00

CPC classification number: H01L45/1253 ,  H01L27/101 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608

Abstract: Embodiments of the invention generally relate to memory devices and methods for fabricating such memory devices. In one embodiment, a method for fabricating a resistive switching memory device includes depositing a metallic layer on a lower electrode disposed on a substrate and exposing the metallic layer to an activated oxygen source while heating the substrate to an oxidizing temperature within a range from about 300° C. to about 600° C. and forming a metal oxide layer from an upper portion of the metallic layer during an oxidation process. The lower electrode contains a silicon material and the metallic layer contains hafnium or zirconium. Subsequent to the oxidation process, the method further includes heating the substrate to an annealing temperature within a range from greater than 600° C. to about 850° C. while forming a metal silicide layer from a lower portion of the metallic layer during a silicidation process.

公开(公告)号：US08501505B2

公开(公告)日：2013-08-06

申请号：US13731715

申请日：2012-12-31

Applicant: Intermolecular, Inc.

Inventor： Guarav Verma ,  Tony P. Chiang ,  Imran Hashim ,  Sandra G. Malhotra ,  Prashant B. Phatak ,  Kurt H. Weiner

IPC: H01L21/00

CPC classification number: G01R31/2831 ,  G01R31/2834 ,  H01L22/34

Abstract: In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions.

公开(公告)号：US20130056101A1

公开(公告)日：2013-03-07

申请号：US13661501

申请日：2012-10-26

Applicant: INTERMOLECULAR, INC.

Inventor： Thomas R. Boussie ,  Tony P. Chiang ,  Alexander Gorer ,  David E. Lazovsky

IPC: F03B11/02

CPC classification number: H01L21/67011 ,  C23C14/54 ,  C23C16/4412 ,  C23C16/45544 ,  C23C16/4557 ,  C23C16/45578 ,  C23C16/4583 ,  C23C16/46 ,  C23C16/52 ,  H01J37/32449 ,  H01J37/32513 ,  H01J37/32724 ,  H01J2237/166 ,  H01J2237/20228 ,  H01J2237/20235 ,  H01L21/6715 ,  H01L21/76849 ,  H01L22/20 ,  H01L2924/0002 ,  Y10S438/907 ,  Y10S438/913 ,  Y10T137/8593 ,  H01L2924/00

Abstract: The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.

Abstract translation: 本发明提供了用于基板区域的离散化，组合处理的方法和系统，例如用于集成电路制造中使用的新材料，工艺和工艺顺序集成方案的发现，实现，优化和鉴定。 通过将材料输送到衬底或修改衬底的区域来处理其上具有差分处理区域阵列的衬底。

公开(公告)号：US20130043454A1

公开(公告)日：2013-02-21

申请号：US13659037

申请日：2012-10-24

Applicant: INTERMOLECULAR, INC.

Inventor： Alexander Gorer ,  Tony P. Chiang ,  Igor Ivanov ,  Prashant B. Phatak

IPC: H01L45/00

CPC classification number: H01L45/10 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1633

Abstract: Non-volatile resistive-switching memories formed using anodization are described. A method for forming a resistive-switching memory element using anodization includes forming a metal containing layer, anodizing the metal containing layer at least partially to form a resistive switching metal oxide, and forming a first electrode over the resistive switching metal oxide. In some examples, an unanodized portion of the metal containing layer may be a second electrode of the memory element.

Abstract translation: 描述了使用阳极氧化形成的非易失性电阻式开关存储器。 一种使用阳极氧化形成电阻式开关存储元件的方法包括形成含金属层，至少部分地阳极氧化含金属层以形成电阻式开关金属氧化物，以及在电阻式开关金属氧化物上形成第一电极。 在一些实例中，含金属层的未渐变部分可以是存储元件的第二电极。

公开(公告)号：US09444047B2

公开(公告)日：2016-09-13

申请号：US14806263

申请日：2015-07-22

Applicant: Intermolecular Inc.

Inventor： Imran Hashim ,  Tony P. Chiang ,  Vidyut Gopal ,  Yun Wang

IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

CPC classification number: H01L45/1608 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2213/32 ,  G11C2213/51 ,  G11C2213/52 ,  G11C2213/74 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146

Abstract: Provided are nonvolatile memory assemblies each including a resistive switching layer and current steering element. The steering element may be a transistor connected in series with the switching layer. Resistance control provided by the steering element allows using switching layers requiring low switching voltages and currents. Memory assemblies including such switching layers are easier to embed into integrated circuit chips having other low voltage components, such as logic and digital signal processing components, than, for example, flash memory requiring much higher switching voltages. In some embodiments, provided nonvolatile memory assemblies operate at switching voltages less than about 3.0V and corresponding currents less than 50 microamperes. A memory element may include a metal rich hafnium oxide disposed between a titanium nitride electrode and doped polysilicon electrode. One electrode may be connected to a drain or source of the transistor, while another electrode is connected to a signal line.