公开(公告)号：US09760434B2

公开(公告)日：2017-09-12

申请号：US14841950

申请日：2015-09-01

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Chang Huang ,  Ken-Hui Chen ,  Chun-Hsiung Hung

IPC: G06F11/10 ,  G11C29/52 ,  G11C29/04

CPC classification number: G06F11/1068 ,  G06F11/1052 ,  G11C29/52 ,  G11C2029/0411

Abstract: A method of operating a memory device storing ECCs for corresponding data is provided. The method includes writing an extended ECC during a first program operation, the extended ECC including an ECC and an extended bit derived from the ECC. The method includes overwriting the extended ECC with a pre-determined state during a second program operation to indicate the second program operation. The method includes, setting the ECC to an initial ECC state before the first program operation; during the first program operation, computing the ECC, changing the ECC to the initial ECC state if the computed ECC equals the pre-determined state; and changing the extended bit to an initial value if the ECC equals the initial ECC state. The method includes reading an extended ECC including an extended bit and an ECC for corresponding data, and determining whether to enable ECC logic using the extended ECC.

公开(公告)号：US09690650B2

公开(公告)日：2017-06-27

申请号：US13951130

申请日：2013-07-25

Applicant: Macronix International Co., Ltd.

Inventor： Yi-Ching Liu ,  Chi Lo ,  Shuo-Nan Hung ,  Chun-Hsiung Hung

IPC: G11C29/00 ,  G06F11/10 ,  G11B20/18 ,  G11C7/10

CPC classification number: G06F11/1044 ,  G06F11/1008 ,  G06F11/1068 ,  G11B20/1833 ,  G11C7/1006

Abstract: A device includes a memory array storing data and error correcting codes ECCs corresponding to the data, and a multi-level buffer structure between the memory array and an input/output data path. The memory array includes a plurality of data lines for page mode operations. The buffer structure includes a first buffer having storage cells connected to respective data lines in the plurality of data lines for a page of data, a second buffer coupled to the storage cells in the first buffer for storing at least one page of data, and a third buffer coupled to the second buffer and to the input/output data path. The device includes logic coupled to the multi-level buffer to perform a logical process over pages of data during movement between the memory array and the input/output path through the multi-level buffer for at least one of page read and page write operations.

公开(公告)号：US09570186B2

公开(公告)日：2017-02-14

申请号：US14853583

申请日：2015-09-14

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chun-Hsiung Hung ,  Chi Lo

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/06 ,  G11C16/28 ,  G11C11/56 ,  G11C16/10

CPC classification number: G11C16/26 ,  G11C11/56 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/10 ,  G11C16/28 ,  Y10T29/49117

Abstract: Various embodiments address various difficulties with source side sensing difficulties in various memory architectures, such as 3D vertical gate flash and multilevel cell memory. One such difficulty is that with source side sensing, the signal amplitude is significantly smaller than drain side sensing. Another such difficulty is the noise and reduced sensing margins associated with multilevel cell memory. In some embodiments the bit line is selectively discharged prior to applying the read bias arrangement.

Abstract translation: 各种实施例解决了诸如3D垂直门闪存和多电平单元存储器的各种存储器架构中的源侧感测困难的各种困难。 一个这样的困难是，通过源侧感测，信号幅度显着小于漏极侧感测。 另一个这样的困难是与多电平单元存储器相关联的噪声和降低的感测裕度。 在一些实施例中，位线在施加读取偏置布置之前被选择性地放电。

公开(公告)号：US09542268B2

公开(公告)日：2017-01-10

申请号：US14167927

申请日：2014-01-29

Applicant: Macronix International Co., Ltd.

Inventor： Chung-Kuang Chen ,  Han-Sung Chen ,  Chun-Hsiung Hung

IPC: H03M13/00 ,  H03M13/11 ,  G06F11/10 ,  H03M13/15 ,  H03M13/35

CPC classification number: G06F11/1048 ,  H03M13/151 ,  H03M13/356 ,  H03M13/6505 ,  H03M13/6561

Abstract: A method for operating a memory includes receiving an input data set, saving a first level error correcting code ECC for the data in the input data set, saving second level ECCs for a plurality of second level groups of the data in the data set, storing the data set in the memory, and testing the data set to determine whether to use the first level ECC or the second level ECCs. The method includes, if the first level ECC is used, storing a flag enabling use of the first level ECC, else if the second level ECCs are used, storing a flag enabling use of the second level ECCs. The method includes storing the second level ECCs in a replacement ECC memory, and storing a pointer indicating locations of the second level ECCs in the replacement ECC memory.

Abstract translation: 用于操作存储器的方法包括接收输入数据集，为输入数据集中的数据保存第一级纠错码ECC，为数据集中的数据的多个第二级组保存第二级ECC，存储 存储器中的数据集，并测试数据集以确定是使用第一级ECC还是第二级ECC。 该方法包括如果使用第一级ECC，则存储能够使用第一级ECC的标志，否则如果使用第二级ECC，则存储允许使用第二级ECC的标志。 该方法包括将第二级ECC存储在替换ECC存储器中，并将指示第二级ECC的位置的指针存储在替换ECC存储器中。

公开(公告)号：US09536601B2

公开(公告)日：2017-01-03

申请号：US14533936

申请日：2014-11-05

Applicant: Macronix International Co., Ltd.

Inventor： Chung-Kuang Chen ,  Han-Sung Chen ,  Chun-Hsiung Hung

IPC: G11C16/04 ,  G11C11/56 ,  G11C16/10 ,  G11C16/34

CPC classification number: G11C11/5628 ,  G11C16/10 ,  G11C16/3481 ,  G11C2211/5642

Abstract: A memory cell undergoing programming is determined as belonging to a particular one of a plurality of second threshold voltage ranges that divide a present threshold voltage range of the particular memory cell. Programming pulses are applied to program the particular memory cell to within the target threshold voltage range. At least one of a program voltage and a total duration of the programming pulses applied to the particular memory cell is varied, depending on the particular second threshold voltage range of the memory cell.

Abstract translation: 正在进行编程的存储单元被确定为属于划分特定存储单元的当前阈值电压范围的多个第二阈值电压范围中的特定的一个。 施加编程脉冲以将特定存储器单元编程到目标阈值电压范围内。 根据存储单元的特定的第二阈值电压范围，施加到特定存储单元的编程脉冲的编程电压和总持续时间中的至少一个是不同的。

公开(公告)号：US09508455B2

公开(公告)日：2016-11-29

申请号：US14595252

申请日：2015-01-13

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chung-Kuang Chen ,  Han-Sung Chen ,  Chun-Hsiung Hung

IPC: G11C7/10 ,  G11C29/50 ,  G11C29/00

CPC classification number: G11C29/50016 ,  G11C7/02 ,  G11C7/1036 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3427 ,  G11C16/3459 ,  G11C19/00 ,  G11C29/86 ,  G11C2211/5621

Abstract: An operating method of a memory device comprises the following steps: a first page buffer receives a first input data to be programed into a first memory cell of the memory cells; a second page buffer receives a second input data to be programed into a second memory cell of the memory cells; and the first page buffer determines whether to shift a program verify (PV) voltage for the first input data according to the first and second input data.

Abstract translation: 存储器件的操作方法包括以下步骤：第一页缓冲器接收要被编程到存储器单元的第一存储器单元中的第一输入数据; 第二页缓冲器接收要编程到存储器单元的第二存储单元中的第二输入数据; 并且第一页缓冲器根据第一和第二输入数据确定是否移位用于第一输入数据的程序验证（PV）电压。

公开(公告)号：US09502121B2

公开(公告)日：2016-11-22

申请号：US14518645

申请日：2014-10-20

Applicant: Macronix International Co., Ltd.

Inventor： Chun-Yi Lee ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC: G11C16/14 ,  G11C16/16 ,  G11C16/34

CPC classification number: G11C16/14 ,  G11C16/16 ,  G11C16/344

Abstract: Memory cells of a nonvolatile memory array are characterized by one of multiple threshold voltage ranges including at least an erased threshold voltage range and a programmed threshold voltage range. Responsive to an erase command to erase a group of memory cells of the nonvolatile memory array, a plurality of phases are performed, including at least a pre-program phase and an erase phase. The pre-program phase programs a first set of memory cells in the group having threshold voltages within the erased threshold voltage range, and does not program a second set of memory cells in the group having threshold voltages within the erased threshold voltage range in the group. By not programming the second set of memory cells, the pre-program phase is performed more quickly than if the second set of memory cells were programmed along with the first set of memory cells.

Abstract translation: 非易失性存储器阵列的存储单元的特征在于包括至少一个擦除的阈值电压范围和编程的阈值电压范围的多个阈值电压范围之一。 响应于擦除非易失性存储器阵列的一组存储单元的擦除命令，执行至少包括预编程相位和擦除阶段的多个相位。 预编程相位对组内的阈值电压中的第一组存储器单元进行编程，并且不对组中擦除的阈值电压范围内的阈值电压的组中的第二组存储器单元进行编程 。 通过不对第二组存储器单元进行编程，如果第二组存储器单元与第一组存储器单元一起被编程，那么执行预编程相位更快。

公开(公告)号：US09496015B1

公开(公告)日：2016-11-15

申请号：US14822941

申请日：2015-08-11

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Ming-Hsiu Lee ,  Chun-Hsiung Hung ,  Tien-Yen Wang

IPC: G11C11/34 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14

CPC classification number: G11C8/10 ,  G11C8/12 ,  G11C8/14 ,  G11C16/08

Abstract: An array structure includes: a plurality of first signal lines and a plurality of sub-arrays. Each of the sub-array includes: a second signal line, a plurality of third signal lines, a plurality of fourth signal lines, a plurality of local decoders at each intersection of the first signal lines, the second signal line and the third signal lines; and a plurality of array cells at each intersection of the first signal lines, the third signal lines and the fourth signal lines. Respective control terminals of the local decoders are implemented by the first signal lines. In response to a selection status of the first signal lines and the second signal line, one of the local decoders selects one of the third signal lines.

Abstract translation: 阵列结构包括：多个第一信号线和多个子阵列。 每个子阵列包括：第二信号线，多条第三信号线，多条第四信号线，在第一信号线，第二信号线和第三信号线的每个交叉处的多个本地解码器 ; 以及在第一信号线，第三信号线和第四信号线的每个交叉处的多个阵列单元。 本地解码器的各控制端由第一信号线实现。 响应于第一信号线和第二信号线的选择状态，本地解码器之一选择第三信号线之一。

公开(公告)号：US09450577B1

公开(公告)日：2016-09-20

申请号：US14742160

申请日：2015-06-17

Applicant: Macronix International Co., Ltd.

Inventor： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen ,  Su-Chueh Lo ,  Tzu-Ting Chiu

IPC: H03K3/00 ,  H03K17/16

CPC classification number: H03K19/018507

Abstract: An output circuit includes: an output switch including a gate terminal, a drain terminal coupled to an external I/O bus, and a well terminal; a well control circuit, having a well terminal coupled to the well terminal of the output switch, to maintain a well voltage of the output switch at a level not less than a greater of a first voltage and a second voltage; and a gate control circuit coupled to the gate terminal and a the drain terminal of the output switch and to the external I/O bus, and operable to turn off the output switch, to prevent current flow through the output switch from the external I/O bus when an operating voltage of the output circuit is not applied to the output switch, and a bus voltage from an external device is present on the external I/O bus.

Abstract translation: 输出电路包括：输出开关，包括栅极端子，耦合到外部I / O总线的漏极端子和阱端子; 阱控制电路，具有耦合到输出开关的阱端子的阱端子，以将输出开关的阱电压保持在不小于第一电压和第二电压的较大值的水平; 以及栅极控制电路，其耦合到输出开关的栅极端子和漏极端子和外部I / O总线，并且可操作以关闭输出开关，以防止电流从外部I / O总线流过输出开关， O总线时，输出电路的工作电压不被施加到输出开关，并且来自外部设备的总线电压存在于外部I / O总线上。

公开(公告)号：US09444462B2

公开(公告)日：2016-09-13

申请号：US14458936

申请日：2014-08-13

Applicant: Macronix International Co., Ltd.

Inventor： Yu-Meng Chaung ,  Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen

IPC: H03K3/00 ,  H03K19/0185 ,  H03K19/003

CPC classification number: H03K19/018521 ,  H03K19/00384

Abstract: An integrated circuit includes an output buffer and a control circuit. The output buffer has a signal input, a signal output, and a set of control inputs. The output buffer has an output buffer delay, and a driving strength adjustable in response to control signals applied to the set of control inputs. Alternatively, the output buffer delay is variable. The control circuit is connected to the set of control inputs of the output buffer. The control circuit uses first and second timing signals to generate the control signals, and can include a first delay circuit that generates the first timing signal with a first delay, and a second delay circuit that generates the second timing signal with a second delay that correlates with the output buffer delay.

Abstract translation: 集成电路包括输出缓冲器和控制电路。 输出缓冲器具有信号输入，信号输出和一组控制输入。 输出缓冲器具有输出缓冲器延迟，并且响应于施加到该组控制输入的控制信号而可调整驱动强度。 或者，输出缓冲器延迟是可变的。 控制电路连接到输出缓冲器的一组控制输入。 控制电路使用第一和第二定时信号来产生控制信号，并且可以包括产生具有第一延迟的第一定时信号的第一延迟电路和产生具有第二延迟的第二定时信号的第二延迟电路， 与输出缓冲区延迟。