公开(公告)号：US20250022804A1

公开(公告)日：2025-01-16

申请号：US18902765

申请日：2024-09-30

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Kunal R. Parekh

IPC: H01L23/538 ,  H01L21/50 ,  H01L21/768 ,  H01L27/06 ,  H01L27/092

Abstract: Systems and methods for a semiconductor device having a substrate material with a trench at a front side, a conformal dielectric material over at least a portion of the front side of the substrate material and in the trench, a fill dielectric material on the conformal dielectric material in the trench, and a conductive portion formed during front-end-of-line (FEOL) processing. The conductive portion may include an FEOL interconnect via extending through the fill dielectric material and at least a portion of the conformal dielectric material and having a front side portion defining a front side electrical connection extending beyond the front side of the semiconductor substrate material and a backside portion defining an active contact surface. The conductive portion may extend across at least a portion of the conformal dielectric material and the fill dielectric material and have a backside surface defining an active contact surface.

公开(公告)号：US20240420757A1

公开(公告)日：2024-12-19

申请号：US18820840

申请日：2024-08-30

Applicant: Micron Technology, Inc.

Inventor： Glen E. Hush ,  Sean S. Eilert ,  Aliasger T. Zaidy ,  Kunal R. Parekh

IPC: G11C11/4093 ,  G06F3/06 ,  G06F13/16 ,  G06F13/28 ,  G11C7/08 ,  G11C7/10 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4096 ,  G16B30/00 ,  G16B50/10 ,  H01L21/66 ,  H01L21/78 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

Abstract: A memory device includes an array of memory cells configured on a die or chip and coupled to sense lines and access lines of the die or chip and a respective sense amplifier configured on the die or chip coupled to each of the sense lines. Each of a plurality of subsets of the sense lines is coupled to a respective local input/output (I/O) line on the die or chip for communication of data on the die or chip and a respective transceiver associated with the respective local I/O line, the respective transceiver configured to enable communication of the data to one or more device off the die or chip.

公开(公告)号：US20240355371A1

公开(公告)日：2024-10-24

申请号：US18607033

申请日：2024-03-15

Applicant: Micron Technology, Inc.

Inventor： James Brian Johnson ,  Brent Keeth ,  Kunal R. Parekh ,  Eiichi Nakano ,  Amy Rae Griffin

IPC: G11C7/10 ,  G11C7/22 ,  G11C29/52

CPC classification number: G11C7/1069 ,  G11C7/222 ,  G11C29/52

Abstract: Methods, systems, and devices for data path signal amplification in coupled semiconductor systems are described. A semiconductor system may implement a first die including memory arrays and a second die including a host interface. The first die may include a first portion of a data path between the memory arrays and the host interface, including a first portion of data path signal amplification circuitry. The second die may include a second portion of the data path, including a second portion of data path signal amplification circuitry. The semiconductor system may implement fine-pitch interconnection between dies to support a relatively greater quantity of signal paths of the data path which, in some examples, may support reducing or eliminating serialization/deserialization circuitry associated with coarser interconnection. In some implementations, a semiconductor system may implement a switching component operable to switch between data paths having different amplification configurations of the dies.

公开(公告)号：US20240339433A1

公开(公告)日：2024-10-10

申请号：US18610268

申请日：2024-03-20

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Nevil N. Gajera ,  Akshay N. Singh ,  Kunal R. Parekh

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L25/00 ,  H10B80/00

CPC classification number: H01L25/0652 ,  H01L23/31 ,  H01L23/481 ,  H01L24/08 ,  H01L24/19 ,  H01L24/20 ,  H01L24/80 ,  H01L24/94 ,  H01L25/50 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2224/19 ,  H01L2224/21 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/94 ,  H01L2225/06548

Abstract: A semiconductor device with a through dielectric via is disclosed. The semiconductor device assembly can include a semiconductor die and multiple stacks of semiconductor dies coupled with the semiconductor die at different lateral locations. Dielectric material can be disposed at the semiconductor die between the multiple stacks of semiconductor dies. The through dielectric via can extend entirely through the dielectric material to the semiconductor die such that the through dielectric via couples with circuitry at the semiconductor die. In this way, the through dielectric via can provide power to the semiconductor die (e.g., exclusive of the multiple stacks of semiconductor dies).

公开(公告)号：US12089422B2

公开(公告)日：2024-09-10

申请号：US18460358

申请日：2023-09-01

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh

IPC: H10B41/27 ,  G11C5/06 ,  H01L25/16 ,  H01L25/18 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B63/00 ,  H10N70/00

CPC classification number: H10B63/84 ,  G11C5/063 ,  H01L25/16 ,  H01L25/18 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B63/34 ,  H10N70/011 ,  H10N70/882

Abstract: A method of forming a microelectronic device comprises forming a microelectronic device structure comprising a first control logic region comprising first control logic devices, and a first memory array region vertically overlying the first control logic region and comprising an array of vertically extending strings of memory cells. An additional microelectronic device structure comprising a semiconductive material is attached to an upper surface of the microelectronic device structure. A portion of the semiconductive material is removed. A second control logic region is formed over the first memory array region. The second control logic region comprises second control logic devices and a remaining portion of the semiconductive material. A second memory array region is formed over the second control logic region. The second memory array region comprises an array of resistance variable memory cells. Microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US20240297149A1

公开(公告)日：2024-09-05

申请号：US18426271

申请日：2024-01-29

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Akshay N. Singh ,  Kunal R. Parekh

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H10B80/00

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3128 ,  H01L24/08 ,  H01L24/80 ,  H01L24/94 ,  H01L25/50 ,  H10B80/00 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/08145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/94

Abstract: A semiconductor device assembly is provided. The semiconductor device assembly includes a logic die, a top memory die, and a one or more intermediate memory dies between the top memory die and the logic die. Front sides of the one or more intermediate memory dies at which active circuitry is disposed face a front side of the top memory die. Back sides of the one or more intermediate memory dies opposite the front sides face a back side of the logic die. In doing so, a cost-efficient, low-complexity semiconductor device can be assembled.

公开(公告)号：US20240213150A1

公开(公告)日：2024-06-27

申请号：US18600146

申请日：2024-03-08

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh

IPC: H01L23/522 ,  G11C7/18 ,  H01L23/00 ,  H01L23/528 ,  H01L25/18 ,  H10B41/27 ,  H10B41/35

CPC classification number: H01L23/5226 ,  G11C7/18 ,  H01L23/5283 ,  H01L24/05 ,  H01L25/18 ,  H10B41/27 ,  H10B41/35 ,  H01L2924/1431 ,  H01L2924/1443

Abstract: A method of forming a microelectronic device comprises forming a microelectronic device structure comprising a base structure, a doped semiconductive material overlying the base structure, a stack structure overlying the doped semiconductive material, cell pillar structures vertically extending through the stack structure and the doped semiconductive material and into the base structure, and digit line structures vertically overlying the stack structure. An additional microelectronic device structure comprising control logic devices is formed. The microelectronic device structure is attached to the additional microelectronic device structure to form a microelectronic device structure assembly. The base structure and portions of the cell pillar structures vertically extending into the base structure are removed to expose the doped semiconductive material. The doped semiconductive material is then patterned to form at least one source structure over the stack structure and coupled to the cell pillar structures. Microelectronic devices and electronic systems are also described.

公开(公告)号：US20240186274A1

公开(公告)日：2024-06-06

申请号：US18522457

申请日：2023-11-29

Applicant: Micron Technology, Inc.

Inventor： Amy Rae Griffin ,  Brent Keeth ,  Kunal R. Parekh ,  Eiichi Nakano ,  James Brian Johnson ,  Ameen D. Akel

IPC: H01L23/00 ,  H01L23/29 ,  H01L25/065 ,  H10B80/00

CPC classification number: H01L24/08 ,  H01L23/29 ,  H01L24/80 ,  H01L25/0657 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: Methods, systems, and devices for thermal distribution techniques in coupled semiconductor systems are described. A semiconductor system may be formed by coupling various semiconductor components with one another, and may also implement a semiconductor material to support a thermal path having a thermal conductivity that is relatively close to a thermal conductivity through the coupled semiconductor components of the semiconductor system. Such a semiconductor material may be located in regions of the semiconductor system that are otherwise unoccupied by functional (e.g., electrically operable) semiconductor components and may, in some examples, be electrically inoperable (e.g., may lack functional circuitry). For implementations in which functional semiconductor components are directly coupled (e.g., by fusion bonding or hybrid bonding techniques), the semiconductor material may also be directly coupled with at least one of the semiconductor components.

公开(公告)号：US20240071556A1

公开(公告)日：2024-02-29

申请号：US17821676

申请日：2022-08-23

Applicant: Micron Technology, Inc.

Inventor： James Brian Johnson ,  Kunal R. Parekh ,  Brent Keeth ,  Eiichi Nakano ,  Amy Rae Griffin

IPC: G11C29/56 ,  G11C7/10

CPC classification number: G11C29/56004 ,  G11C7/1039 ,  G11C29/56016 ,  G11C2029/5602

Abstract: Methods, systems, and devices for memory with parallel main and test interfaces are described. A memory die may be configured with parallel interfaces that may individually (e.g., separately) support evaluation operations (e.g., before or as part of assembly in a multiple-die stack) or access operations (e.g., after assembly in a multiple die stack). For example, a memory die may include a first set of one or more contacts that support communicating signaling with or via another memory die in a multiple-die stack. The memory die may also include a second set of one or more contacts that support probing for pre-assembly evaluations, which may be electrically isolated from the first set of contacts. By implementing such parallel interfaces, evaluation operations may be performed using the second set of contacts without damaging the first set of contacts, which may improve capabilities for supporting a multiple-die stack in a memory device.

公开(公告)号：US20240055397A1

公开(公告)日：2024-02-15

申请号：US17884484

申请日：2022-08-09

Applicant: Micron Technology, Inc.

Inventor： Thiagarajan Raman ,  Kunal R. Parekh

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/495 ,  H01L23/492 ,  H01L23/66 ,  H01L23/498

CPC classification number: H01L25/0655 ,  H01L23/5386 ,  H01L23/49575 ,  H01L23/492 ,  H01L23/66 ,  H01L23/49513 ,  H01L23/49805 ,  H01L25/18

Abstract: This document discloses techniques, apparatuses, and systems for providing a semiconductor device assembly with through-substrate connections for recessed semiconductor dies. A semiconductor device assembly is described that includes a substrate having a first cavity and a second cavity. A first connective element is located at a side surface of the first cavity and a second connective element is located at a side surface of the second cavity. The semiconductor device assembly include a first semiconductor die and a second semiconductor die implemented at the first cavity and the second cavity, respectively. The first semiconductor die includes a third connective element at an edge surface of the die. The second semiconductor die includes a fourth connective element at an edge surface of the die. The dies are implemented at the cavities and connected through the connective elements to electrically couple the first die to the second die.