公开(公告)号：US20190252551A1

公开(公告)日：2019-08-15

申请号：US16355398

申请日：2019-03-15

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing LIU ,  John H. Zhang

IPC: H01L29/788 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/7883 ,  H01L27/088 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/7889

Abstract: A semi-floating gate transistor is implemented as a vertical FET built on a silicon substrate, wherein the source, drain, and channel are vertically aligned, on top of one another. Current flow between the source and the drain is influenced by a control gate and a semi-floating gate. Front side contacts can be made to each one of the source, drain, and control gate terminals of the vertical semi-floating gate transistor. The vertical semi-floating gate FET further includes a vertical tunneling FET and a vertical diode. Fabrication of the vertical semi-floating gate FET is compatible with conventional CMOS manufacturing processes, including a replacement metal gate process. Low-power operation allows the vertical semi-floating gate FET to provide a high current density compared with conventional planar devices.

公开(公告)号：US10347617B2

公开(公告)日：2019-07-09

申请号：US15695198

申请日：2017-09-05

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： Lawrence A. Clevenger ,  Carl J. Radens ,  Yiheng Xu ,  John H. Zhang

IPC: H01L21/44 ,  H01L21/48 ,  H01L23/02 ,  H01L25/18 ,  H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L23/13 ,  H01L23/15

Abstract: Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips supported by a scaffolding structure, the scaffolding structure defined by a first scaffolding trench and at least one additional scaffolding trench, the first scaffolding trench comprising a bottom surface having a width and a sidewall having a height extending from the bottom surface to define a lowermost trench in a scaffolding layer, the at least one additional scaffolding trench overlaying the first scaffolding trench having a sidewall having a height and a width, wherein the width of the at least one scaffolding trench is greater than the first scaffolding trench width to define a first stair between the first scaffolding trench and the at least one additional trench; a first chip secured to the first scaffolding trench having a height less than the first scaffolding trench sidewall height; and at least one additional chip secured to and supported by the first stair, wherein the at least one additional chip is vertically spaced apart from the first chip.

公开(公告)号：US20180337133A1

公开(公告)日：2018-11-22

申请号：US15984263

申请日：2018-05-18

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L23/538 ,  H01L29/792 ,  H01L29/786 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/775 ,  H01L29/66 ,  H01L29/423 ,  H01L29/417 ,  H01L29/16 ,  H01L29/06 ,  H01L27/092 ,  H01L27/07 ,  H01L27/06 ,  H01L27/02 ,  H01L27/11582 ,  H01L29/51

CPC classification number: H01L23/5386 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823871 ,  H01L21/823885 ,  H01L23/5384 ,  H01L27/0255 ,  H01L27/0688 ,  H01L27/0705 ,  H01L27/0727 ,  H01L27/092 ,  H01L27/11582 ,  H01L29/0676 ,  H01L29/1608 ,  H01L29/41741 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/7827 ,  H01L29/78642 ,  H01L29/78696 ,  H01L29/7926

Abstract: A modular interconnect structure facilitates building complex, yet compact, integrated circuits from vertical GAA FETs. The modular interconnect structure includes annular metal contacts to the transistor terminals, sectors of stacked discs extending radially outward from the vertical nanowires, and vias in the form of rods. Extension tabs mounted onto the radial sector interconnects permit signals to fan out from each transistor terminal. Adjacent interconnects are linked by linear segments. Unlike conventional integrated circuits, the modular interconnects as described herein are formed at the same time as the transistors. Vertical GAA NAND and NOR gates provide building blocks for creating all types of logic gates to carry out any desired Boolean logic function. Stacked vertical GAA FETs are made possible by the modular interconnect structure. The modular interconnect structure permits a variety of specialized vertical GAA devices to be integrated on a silicon substrate using standard CMOS processes.

公开(公告)号：US10039462B2

公开(公告)日：2018-08-07

申请号：US15651896

申请日：2017-07-17

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: A61B5/04 ,  A61N1/00 ,  A61B5/00 ,  B82Y30/00 ,  G01N27/414

Abstract: It is recognized that, because of its unique properties, graphene can serve as an interface with biological cells that communicate by an electrical impulse, or action potential. Responding to a sensed signal can be accomplished by coupling a graphene sensor to a low power digital electronic switch that is activatable by the sensed low power electrical signals. It is further recognized that low power devices such as tunneling diodes and TFETs are suitable for use in such biological applications in conjunction with graphene sensors. While tunneling diodes can be used in diagnostic applications, TFETs, which are three-terminal devices, further permit controlling the voltage on one cell according to signals received by other cells. Thus, by the use of a biological sensor system that includes graphene nanowire sensors coupled to a TFET, charge can be redistributed among different biological cells, potentially with therapeutic effects.

公开(公告)号：US20180204933A1

公开(公告)日：2018-07-19

申请号：US15920384

申请日：2018-03-13

Applicant: STMICROELECTRONICS, INC.

Inventor： John H. Zhang

IPC: H01L29/66 ,  H01L27/12 ,  H01L21/84 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/7845 ,  H01L29/785

Abstract: Stress is introduced into the channel of an SOI FinFET device by transfer directly from a metal gate. In SOI devices in particular, stress transfer efficiency from the metal gate to the channel is nearly 100%. Either tensile or compressive stress can be applied to the fin channel by choosing different materials to be used in the gate stack as the bulk gate material, a gate liner, or a work function material, or by varying processing parameters during deposition of the gate or work function materials. P-gates and N-gates are therefore formed separately. Gate materials suitable for use as stressors include tungsten (W) for NFETs and titanium nitride (TiN) for PFETs. An optical planarization material assists in patterning the stress-inducing metal gates. A simplified process flow is disclosed in which isolation regions are formed without need for a separate mask layer, and gate sidewall spacers are not used.

公开(公告)号：US09953983B2

公开(公告)日：2018-04-24

申请号：US15482610

申请日：2017-04-07

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L21/00 ,  H01L21/8238 ,  H01L21/336 ,  H01L31/0328 ,  H01L29/80 ,  H01L27/108 ,  H01L29/66 ,  H01L31/0392 ,  H01L29/06 ,  H01L45/00 ,  H01L29/78 ,  H01L33/04

CPC classification number: H01L27/10879 ,  B82Y10/00 ,  H01L21/28008 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/823885 ,  H01L21/823892 ,  H01L27/0814 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/0653 ,  H01L29/0676 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/20 ,  H01L29/42392 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/66909 ,  H01L29/66977 ,  H01L29/7391 ,  H01L29/775 ,  H01L29/7827 ,  H01L29/7855 ,  H01L29/7856 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696 ,  H01L31/0392 ,  H01L33/04 ,  H01L45/1233 ,  H01L2029/7858

Abstract: A vertical tunneling FET (TFET) provides low-power, high-speed switching performance for transistors having critical dimensions below 7 nm. The vertical TFET uses a gate-all-around (GAA) device architecture having a cylindrical structure that extends above the surface of a doped well formed in a silicon substrate. The cylindrical structure includes a lower drain region, a channel, and an upper source region, which are grown epitaxially from the doped well. The channel is made of intrinsic silicon, while the source and drain regions are doped in-situ. An annular gate surrounds the channel, capacitively controlling current flow through the channel from all sides. The source is electrically accessible via a front side contact, while the drain is accessed via a backside contact that provides low contact resistance and also serves as a heat sink. Reliability of vertical TFET integrated circuits is enhanced by coupling the vertical TFETs to electrostatic discharge (ESD) diodes.

公开(公告)号：US09837394B2

公开(公告)日：2017-12-05

申请号：US14956834

申请日：2015-12-02

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： Lawrence A. Clevenger ,  Carl J. Radens ,  Yiheng Xu ,  John H. Zhang

IPC: H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L25/18 ,  H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L21/48

CPC classification number: H01L25/18 ,  H01L21/4846 ,  H01L23/13 ,  H01L23/147 ,  H01L23/3107 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5389 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15156 ,  H01L2924/15313 ,  H01L2924/157

Abstract: Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips supported by a scaffolding structure, the scaffolding structure defined by a first scaffolding trench and at least one additional scaffolding trench, the first scaffolding trench comprising a bottom surface having a width and a sidewall having a height extending from the bottom surface to define a lowermost trench in a scaffolding layer, the at least one additional scaffolding trench overlaying the first scaffolding trench having a sidewall having a height and a width, wherein the width of the at least one scaffolding trench is greater than the first scaffolding trench width to define a first stair between the first scaffolding trench and the at least one additional trench; a first chip secured to the first scaffolding trench having a height less than the first scaffolding trench sidewall height; and at least one additional chip secured to and supported by the first stair, wherein the at least one additional chip is vertically spaced apart from the first chip.

公开(公告)号：US09806022B2

公开(公告)日：2017-10-31

申请号：US15499665

申请日：2017-04-27

Applicant: STMICROELECTRONICS, INC.

Inventor： John H. Zhang

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5228 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L27/0676 ,  H01L27/0682 ,  H01L27/0802 ,  H01L28/20 ,  H01L28/24 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for making a semiconductor device may include forming a first dielectric layer above a semiconductor substrate, forming a first trench in the first dielectric layer, filling the first trench with electrically conductive material, removing upper portions of the electrically conductive material to define a lower conductive member with a recess thereabove, forming a filler dielectric material in the recess to define a second trench. The method may further include filling the second trench with electrically conductive material to define an upper conductive member, forming a second dielectric layer over the first dielectric layer and upper conductive member, forming a first via through the second dielectric layer and underlying filler dielectric material to the lower conductive member, and forming a second via through the second dielectric layer to the upper conductive member.

公开(公告)号：US09799776B2

公开(公告)日：2017-10-24

申请号：US14739634

申请日：2015-06-15

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  John H. Zhang

IPC: H01L29/788 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L29/7883 ,  H01L27/088 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/7889

Abstract: A semi-floating gate transistor is implemented as a vertical FET built on a silicon substrate, wherein the source, drain, and channel are vertically aligned, on top of one another. Current flow between the source and the drain is influenced by a control gate and a semi-floating gate. Front side contacts can be made to each one of the source, drain, and control gate terminals of the vertical semi-floating gate transistor. The vertical semi-floating gate FET further includes a vertical tunneling FET and a vertical diode. Fabrication of the vertical semi-floating gate FET is compatible with conventional CMOS manufacturing processes, including a replacement metal gate process. Low-power operation allows the vertical semi-floating gate FET to provide a high current density compared with conventional planar devices.

公开(公告)号：US20170278979A1

公开(公告)日：2017-09-28

申请号：US15620444

申请日：2017-06-12

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L29/786 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/12 ,  H01L29/40 ,  H01L29/41 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/778 ,  H01L29/165 ,  H01L29/45 ,  H01L29/49

CPC classification number: H01L29/78618 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/127 ,  H01L29/165 ,  H01L29/401 ,  H01L29/413 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42392 ,  H01L29/456 ,  H01L29/4975 ,  H01L29/66431 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7781 ,  H01L29/78696

Abstract: Metal quantum dots are incorporated into doped source and drain regions of a MOSFET array to assist in controlling transistor performance by altering the energy gap of the semiconductor crystal. In a first example, the quantum dots are incorporated into ion-doped source and drain regions. In a second example, the quantum dots are incorporated into epitaxially doped source and drain regions.