公开(公告)号：US09461564B2

公开(公告)日：2016-10-04

申请号：US14009325

申请日：2012-03-26

Applicant: Thomas Skotnicki

Inventor： Thomas Skotnicki

IPC: H02N2/18 ,  H02N11/00 ,  F03G7/06 ,  H01L41/113

CPC classification number: H02N11/002 ,  F03G7/065 ,  H01L41/113 ,  H01L41/1134 ,  H01L41/183 ,  H02N2/18

Abstract: A thermo-mechano-electric converter including a plurality of shape memory bistable elements embedded in a resilient material intimately associated with a piezoelectric material.

Abstract translation: 一种热机电转换器，其包括嵌入与压电材料紧密相关的弹性材料中的多个形状记忆双稳态元件。

公开(公告)号：US09460923B2

公开(公告)日：2016-10-04

申请号：US14220406

申请日：2014-03-20

Applicant: STMicroelectronics (Crolles 2) SAS ,  Commissariat à l'Énergie Atomique et aux Énergies Alternatives

Inventor： Aomar Halimaoui ,  Jean-Michel Hartmann

IPC: H01L21/02 ,  H01L29/10 ,  H01L21/8238 ,  H01L21/84

CPC classification number: H01L21/02694 ,  H01L21/02002 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/823807 ,  H01L21/84 ,  H01L29/1054

Abstract: The present disclosure concerns a method involving: forming a strained silicon germanium layer by epitaxial growth over a silicon layer disposed on a substrate; implanting atoms to amorphize the silicon layer and a lower portion of the silicon germanium layer, without amorphizing a surface portion of the silicon germanium layer; and annealing, to at least partially relax the silicon germanium layer and to re-crystallize the lower portion of the silicon germanium layer and the silicon layer, so that the silicon layer becomes a strained silicon layer.

Abstract translation: 本公开涉及一种方法，涉及：通过在布置在衬底上的硅层上外延生长来形成应变硅锗层; 注入原子以使硅层和硅锗层的下部非晶化，而不使硅锗层的表面部分非晶化; 并进行退火，以至少部分地使硅锗层松弛并使硅锗层和硅层的下部重新结晶，使得硅层变成应变硅层。

公开(公告)号：US09453723B1

公开(公告)日：2016-09-27

申请号：US14754747

申请日：2015-06-30

Applicant: STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Patrick LeMaitre ,  Jean-Francois Carpentier

IPC: G01B11/26 ,  G01B11/27

CPC classification number: G01B11/27 ,  G01R31/31728 ,  G02B6/12019

Abstract: A method is for testing a photonic integrated circuit (IC) that includes a test structure having a test optical splitter, a test optical input, and first and second test optical outputs. A device under test (DUT) is coupled between the first test optical output and the first output of the test optical splitter. The deembedding structure includes a deembedding optical splitter, a deembedding optical input and first and second deembedding optical outputs. The method includes coupling a test probe device to the test optical inputs and outputs and the deembedding optical inputs and outputs and operating the test probe device to make at least one test measurement related to the DUT and at least one deembedding measurement. The at least one test measurement is processed with the at least one deembedding measurement to determine whether the DUT is acceptable and independent of alignment error.

Abstract translation: 一种用于测试包括具有测试光分路器，测试光输入以及第一和第二测试光输出的测试结构的光子集成电路（IC）的方法。 被测设备（DUT）耦合在第一测试光输出端和测试光分路器的第一输出端之间。 该装饰结构包括一个嵌入式光分路器，一个嵌入式光输入端和第一和第二嵌入式光输出端。 该方法包括将测试探针装置耦合到测试光输入和输出以及去嵌入光输入和输出，并操作测试探针装置以进行至少一个与DUT相关的测试测量和至少一个去镶嵌测量。 用至少一个去镶嵌测量来处理至少一个测试测量，以确定DUT是否可接受并且不依赖于对准误差。

公开(公告)号：US09450000B2

公开(公告)日：2016-09-20

申请号：US14462724

申请日：2014-08-19

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Michel Marty ,  Sebastien Jouan ,  Laurent Frey ,  Salim Boutami

IPC: H01L31/062 ,  H01L27/144 ,  H01L31/0232 ,  H01L27/146 ,  H01L31/107 ,  H01L29/16 ,  H01L29/49 ,  H01L29/66 ,  H01L31/101 ,  H01L31/18

CPC classification number: H01L27/1443 ,  H01L27/14625 ,  H01L27/14643 ,  H01L27/14689 ,  H01L29/16 ,  H01L29/4916 ,  H01L29/6656 ,  H01L31/02327 ,  H01L31/1016 ,  H01L31/107 ,  H01L31/1804

Abstract: A photodiode includes at least one central pad arranged on a light-receiving surface of a photodiode semiconductor substrate. The pad is made of a first material and includes lateral sidewalls surrounded by a spacer made of a second material having a different optical index than the first material. The lateral dimensions of the pad are smaller than an operating wavelength of the photodiode. Both the first and second materials are transparent to that operating wavelength. The pads and spacers are formed at a same time gate electrodes and sidewall spacers of MOS transistors are formed.

Abstract translation: 光电二极管包括布置在光电二极管半导体衬底的光接收表面上的至少一个中心衬垫。 衬垫由第一材料制成，并且包括由具有与第一材料不同的光学折射率的第二材料制成的间隔件包围的侧壁。 焊盘的横向尺寸小于光电二极管的工作波长。 第一和第二材料都对该工作波长是透明的。 焊盘和间隔物同时形成栅电极和MOS晶体管的侧壁间隔物。

公开(公告)号：US09444371B2

公开(公告)日：2016-09-13

申请号：US14378267

申请日：2013-02-13

Applicant: Commissariat a l'energie atomique et aux ene alt ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Emmanuel Ollier ,  Stephane Monfray ,  Thomas Skotnicki ,  Ulrich Soupremanien

IPC: H02N2/18 ,  H01L41/047 ,  H01L41/08

CPC classification number: H02N2/185 ,  H01L41/047 ,  H01L41/08 ,  H02N2/18

Abstract: A device for converting heat energy into electrical energy including cells, the cells including: a first cavity with one wall for contacting a heat source; a second cavity with one wall for contacting a cold source; a primary channel between the first cavity and the second cavity transporting a fluid as liquid drops, the primary channel providing transport of liquid fluid drops from the second cavity to the first cavity; at least one secondary channel between the first cavity and the second cavity transporting the fluid as a gas; a piezoelectric material provided in one of the cavities; and a fluid as a liquid and gas contained within the cell.

Abstract translation: 一种用于将热能转换成包括电池的电能的装置，所述电池包括：具有用于接触热源的一个壁的第一腔; 具有用于接触冷源的一个壁的第二腔; 所述第一腔和所述第二腔之间的主要通道以液体的形式输送流体，所述主要通道提供液体流体液体从所述第二腔向所述第一腔的输送; 所述第一腔和所述第二腔之间的至少一个次通道作为气体输送所述流体; 设置在其中一个空腔中的压电材料; 以及作为包含在电池内的液体和气体的流体。

公开(公告)号：US20160181382A1

公开(公告)日：2016-06-23

申请号：US14577656

申请日：2014-12-19

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Didier Dutartre ,  David Barge

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/786 ,  H01L29/10

CPC classification number: H01L29/41783 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78654

Abstract: A method for forming a transistor includes defining agate structure on a top surface of a first semiconductor layer of a silicon-on-insulator (SOI) substrate. The gate structure includes an insulating cover. A second semiconductor layer is then conformally deposited. The deposited second semiconductor layer includes an epitaxial portion on surfaces of the first semiconductor layer and an amorphous portion on surfaces of the insulating cover. The amorphous portion is then removed using a selective etch. The remaining epitaxial portion forms faceted raised source-drain structures on either side of the transistor gate structure. A slope of the sloped surface for the facet is dependent on the process parameters used during the conformal deposition.

Abstract translation: 一种用于形成晶体管的方法包括在绝缘体上硅（SOI）衬底的第一半导体层的顶表面上限定玛瑙结构。 门结构包括绝缘盖。 然后共形沉积第二半导体层。 沉积的第二半导体层包括在第一半导体层的表面上的外延部分和绝缘盖表面上的非晶部分。 然后使用选择性蚀刻除去非晶部分。 剩余的外延部分在晶体管栅极结构的任一侧上形成刻面凸起的源极 - 漏极结构。 用于小平面的倾斜表面的斜率取决于在保形沉积期间使用的工艺参数。

公开(公告)号：US09356094B2

公开(公告)日：2016-05-31

申请号：US13907547

申请日：2013-05-31

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Aomar Halimaoui ,  Daniel Bensahel

IPC: H01L21/20 ,  H01L29/02 ,  H01L29/06 ,  H01L21/762 ,  H01L21/764 ,  H01L21/02

CPC classification number: H01L29/0649 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02658 ,  H01L21/76262 ,  H01L21/764

Abstract: A method for making a silicon layer extending on an insulation layer, including the steps of forming a silicon-germanium layer on at least a portion of a silicon wafer; transforming portions of the silicon-germanium layer into porous silicon pads; growing a monocrystalline silicon layer on the silicon-germanium layer and on the porous silicon pads; removing the silicon-germanium layer; oxidizing the porous silicon pads; and depositing an insulation material on the silicon layer.

公开(公告)号：US09293429B2

公开(公告)日：2016-03-22

申请号：US13554831

申请日：2012-07-20

Applicant: Laurent-Luc Chapelon

Inventor： Laurent-Luc Chapelon

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/683 ,  H01L23/31

CPC classification number: H01L24/05 ,  H01L21/6835 ,  H01L23/3192 ,  H01L23/481 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/1301 ,  H01L2224/13022 ,  H01L2224/13147 ,  H01L2924/01029 ,  H01L2924/15311

Abstract: An electronic chip including a semiconductor substrate (1) covered with an insulating layer (4) including metal interconnection levels (3) and interconnection pillars (10) connected to said metal interconnection levels (3), said pillars (110) forming regions (111) protruding from the upper surface of said insulating layer (4) and capable of forming an electric contact, wherein said pillars (110) have a built-in portion (115) in a housing formed across the thickness of at least said insulating layer (4).

Abstract translation: 一种电子芯片，其包括覆盖有绝缘层（4）的半导体衬底（1），所述绝缘层包括连接到所述金属互连层（3）的金属互连层（3）和互连柱（10），所述柱（110）形成区域 ）从所述绝缘层（4）的上表面突出并且能够形成电接触，其中所述支柱（110）在形成在至少所述绝缘层的厚度上的壳体中具有内置部分（115） 4）。

公开(公告)号：US20160079388A1

公开(公告)日：2016-03-17

申请号：US14855834

申请日：2015-09-16

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Christian ARVET ,  Sébastien BARNOLA ,  Sébastien LAGRASTA ,  Nicolas POSSEME

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/51 ,  H01L21/283 ,  H01L21/311

CPC classification number: H01L29/6656 ,  H01L21/02326 ,  H01L21/0234 ,  H01L21/283 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/42364 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66628

Abstract: The production of spacers at flanks of a transistor gate, including a step of forming a dielectric layer covering the gate and a peripheral region of a layer of semiconductor material surrounding the gate, including forming a superficial layer covering the gate and the peripheral region; partially removing the superficial layer configured so as to completely remove the superficial layer at the peripheral region while preserving a residual part of the superficial layer at the flanks; and selective etching of the dielectric layer vis-à-vis the material of the residual part of the superficial layer and vis-à-vis the semiconductor material.

Abstract translation: 在晶体管栅极的侧面制造间隔物，包括形成覆盖栅极的介电层和围绕栅极的半导体材料层的外围区域的步骤，包括形成覆盖栅极和外围区域的表面层; 部分去除表层，构造成在外围区域完全除去表层，同时在侧面保留表层的残留部分; 并且相对于表层的残余部分的材料和相对于半导体材料的材料的电介质层的选择性蚀刻。

公开(公告)号：US09240325B2

公开(公告)日：2016-01-19

申请号：US14498091

申请日：2014-09-26

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS SA ,  STMICROELECTRONICS (Crolles 2) SAS

Inventor： Sébastien Barnola ,  Yves Morand ,  Heimanu Niebojewski

IPC: H01L29/423 ,  H01L29/78 ,  H01L21/283 ,  H01L29/66 ,  H01L21/28 ,  H01L29/49

CPC classification number: H01L29/42372 ,  H01L21/28008 ,  H01L21/28052 ,  H01L21/28123 ,  H01L21/283 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/45 ,  H01L29/49 ,  H01L29/4933 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/78

Abstract: A method includes making a gate stack on the surface of an active zone, including depositing a first dielectric layer; depositing a gate conductive layer; depositing a first metal layer; depositing a second metal layer; depositing a second dielectric layer; partially etching the gate stack for the formation of a gate zone on the active zone; making insulating spacers on either side of the gate zone on the active zone; making source and drain electrodes zones; making silicidation zones on the surface of the source and drain zones; etching, in the gate zone on the active zone, the second dielectric layer and the second metal layer with stopping on the first metal layer, so as to form a cavity between the insulating spacers; making a protective plug at the surface of the first metal layer of the gate zone on the active zone, where the protective plug fills the cavity.

Abstract translation: 一种方法包括在有源区的表面上形成栅极堆叠，包括沉积第一介电层; 沉积栅极导电层; 沉积第一金属层; 沉积第二金属层; 沉积第二电介质层; 部分地蚀刻栅极堆叠以在有源区上形成栅极区; 在活动区域​​上的栅极区域的任一侧上制造绝缘垫片; 制造源极和漏极区域; 在源极和漏极区域的表面上形成硅化物区域; 在活性区域的栅极区域中蚀刻在第一金属层上停止的第二介电层和第二金属层，以在绝缘间隔物之间​​形成空腔; 在活动区域​​上的栅极区域的第一金属层的表面上形成保护塞，其中保护塞填充空腔。