公开(公告)号：US10157827B2

公开(公告)日：2018-12-18

申请号：US15196371

申请日：2016-06-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries, Inc.

Inventor： Cheng Chi ,  Ruilong Xie

IPC: H01L23/522 ,  H01L29/417 ,  H01L23/528 ,  H01L23/485 ,  H01L21/8238 ,  H01L21/311 ,  H01L27/12 ,  H01L29/66

Abstract: A method for forming a semiconductor device comprises forming a gate stack on a channel region of a semiconductor, forming a source/drain region adjacent to the channel region, depositing a first insulator layer over the source/drain region, and removing a portion of the first insulator layer to form a first cavity that exposes a portion of the source/drain region. A first conductive material is deposited in the first cavity, and a conductive extension is formed from the first conductive material over the first insulator layer. A protective layer is deposited over the extension and a second insulator layer is deposited over the protective layer. A portion of the second insulator layer is removed to form a second cavity that exposes the protective layer, and an exposed portion of the protective layer is removed to expose a portion of the extension. A second conductive material is deposited in the second cavity.

公开(公告)号：US20180342427A1

公开(公告)日：2018-11-29

申请号：US15602225

申请日：2017-05-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Chanro Park ,  Min Gyu Sung ,  Hoon Kim ,  Hui Zang ,  Guowei Xu

IPC: H01L21/8238 ,  H01L21/3213 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L21/823878 ,  B82Y10/00 ,  H01L21/02603 ,  H01L21/823828 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: This disclosure relates to a method of replacement metal gate patterning for nanosheet devices including: forming a first and a second nanosheet stack on a substrate, the first and the second nanosheet stacks being adjacent to each other and each including vertically adjacent nanosheets separated by a distance; depositing a first metal surrounding the first nanosheet stack and a second portion of the first metal surrounding the second nanosheet stack; forming an isolation region between the first nanosheet stack and the second nanosheet stack; removing the second portion of the first metal surrounding the second nanosheet stack with an etching process, the isolation region preventing the etching process from reaching the first portion of the first metal and thereby preventing removal of the first portion of the first metal; and depositing a second metal surrounding each of the nanosheets of the second nanosheet stack.

公开(公告)号：US20180286956A1

公开(公告)日：2018-10-04

申请号：US15477565

申请日：2017-04-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Andre P. Labonte ,  Lars W. Liebmann ,  Nigel G. Cave ,  Mark V. Raymond ,  Guillaume Bouche ,  David E. Brown

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L21/768 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/3213

CPC classification number: H01L29/41775 ,  H01L21/32139 ,  H01L21/76805 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/42376 ,  H01L29/45 ,  H01L29/66545

Abstract: One illustrative device disclosed herein includes, among other things, a stepped conductive source/drain structure with a first recess defined therein and a stepped final gate structure with a second recess defined therein, wherein, when viewed from above, the second recess is axially and laterally offset from the first recess. In this example, the device also includes a layer of insulating material positioned above the stepped conductive source/drain structure and the stepped final gate structure, a conductive gate (CB) contact that is conductively coupled to the stepped final gate structure and a conductive source/drain (CA) contact that is conductively coupled to the stepped conductive source/drain structure.

公开(公告)号：US10090202B2

公开(公告)日：2018-10-02

申请号：US15357287

申请日：2016-11-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Balasubramanian Pranatharthiharan ,  Junli Wang ,  Ruilong Xie

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06

Abstract: A method of forming a semiconductor device that includes providing a first set of fin structures having a first pitch, and a second set of fin structure having a second pitch, wherein the second pitch is greater than the first pitch. An epitaxial semiconductor material on the first and second set of fin structures. The epitaxial semiconductor material on the first fin structures is merging epitaxial material and the epitaxial material on the second fin structures is non-merging epitaxial material. A dielectric liner is formed atop the epitaxial semiconductor material that is present on the first and second sets of fin structures. The dielectric liner is removed from a portion of the non-merging epitaxial material that is present on the second set of fin structures. A bridging epitaxial semiconductor material is formed on exposed surfaces of the non-merging epitaxial material.

公开(公告)号：US20180277645A1

公开(公告)日：2018-09-27

申请号：US15470205

申请日：2017-03-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Min Gyu Sung

IPC: H01L29/423 ,  H01L21/8234 ,  H01L21/28 ,  H01L29/417

Abstract: Structures involving a field-effect transistor and methods for forming a structure that involves a field-effect transistor. A first metal gate electrode and a second metal gate electrode are formed that are embedded in a first dielectric layer. A second dielectric layer is formed on the first metal gate electrode, the second metal gate electrode, and the first dielectric layer. An opening is formed in the second dielectric layer that extends in a vertical direction to expose a section of the first metal gate electrode. The section of the first metal gate electrode is removed, while the second metal gate electrode is masked by the second dielectric layer, to define a gate cut at a location of the opening. The gate cut may be subsequently filled by dielectric material.

公开(公告)号：US10083861B2

公开(公告)日：2018-09-25

申请号：US15625360

申请日：2017-06-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Huiming Bu ,  Andrew M. Greene ,  Balasubramanian Pranatharthiharan ,  Ruilong Xie

IPC: H01L21/768 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/02 ,  H01L27/088 ,  H01L21/311

CPC classification number: H01L21/823475 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/31111 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/76837 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/41783 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795

Abstract: A method for filling gaps between structures includes forming a plurality of high aspect ratio structures adjacent to one another with gaps, forming a first dielectric layer on tops of the structures and conformally depositing a spacer dielectric layer over the structures. The spacer dielectric layer is removed from horizontal surfaces and a protection layer is conformally deposited over the structures. The gaps are filled with a flowable dielectric, which is recessed to a height along sidewalls of the structures by a selective etch process such that the protection layer protects the spacer dielectric layer on sidewalls of the structures. The first dielectric layer and the spacer dielectric layer are exposed above the height using a higher etch resistance than the protection layer to maintain dimensions of the spacer layer dielectric through the etching processes. The gaps are filled by a high density plasma fill.

公开(公告)号：US10079173B2

公开(公告)日：2018-09-18

申请号：US15285092

申请日：2016-10-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Lars Liebmann ,  Daniel Chanemougame ,  Geng Han

IPC: H01L29/768 ,  H01L23/528 ,  H01L21/768 ,  H01L21/02 ,  H01L29/40 ,  H01L23/522

CPC classification number: H01L21/76816 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76832 ,  H01L21/76835 ,  H01L21/76861 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/823431 ,  H01L21/823821 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/401

Abstract: One illustrative method disclosed includes, among other things, forming a layer of insulating material comprising a first insulating material above a substrate and forming a metallization blocking structure in the layer of insulating material at a location that is in a path of a metallization trench to be formed in the layer of insulating material, the metallization blocking structure comprising a second insulating material that is different from the first insulating material. The method also includes forming the metallization trench in the layer of insulating material on opposite sides of the metallization blocking structure and forming a conductive metallization line in the metallization trench on opposite sides of the metallization blocking structure.

公开(公告)号：US20180261514A1

公开(公告)日：2018-09-13

申请号：US15455203

申请日：2017-03-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Laertis Economikos ,  Chanro Park ,  Min Gyu Sung

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/324 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L21/823828 ,  H01L21/324 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Disclosed are method embodiments for forming an integrated circuit (IC) structure with at least one first-type FINFET and at least one second-type FINFET, wherein the first-type FINFET has a first replacement metal gate (RMG) adjacent to a first semiconductor fin, the second-type FINFET has a second RMG adjacent to a second semiconductor fin, and the first RMG is in end-to-end alignment with the second RMG and physically and electrically isolated from the second RMG by a dielectric column. The method embodiments minimize the risk of the occurrence defects within the RMGs by forming the dielectric column during formation of the first and second RMGs and, particularly, after deposition and anneal of a gate dielectric layer for the first and second RMGs, but before deposition of at least one of multiple work function metal layers. Also disclosed herein are IC structure embodiments formed according to the above-described method embodiments.

公开(公告)号：US10074564B2

公开(公告)日：2018-09-11

申请号：US15878486

申请日：2018-01-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Daniel Chanemougame ,  Ruilong Xie ,  Lars Liebmann

IPC: H01L29/417 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/28 ,  H01L27/092 ,  H01L29/66 ,  H01L23/522 ,  H01L29/40 ,  H01L29/78 ,  H01L23/528

CPC classification number: H01L21/76897 ,  H01L21/28247 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66613 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: Disclosed are methods and integrated circuit (IC) structures. The methods enable formation of a gate contact on a gate above (or close thereto) an active region of a field effect transistor (FET) and provide protection against shorts between the gate contact and metal plugs on source/drain regions and between the gate and source/drain contacts to the metal plugs. A gate with a dielectric cap and dielectric sidewall spacer is formed on a FET channel region. Metal plugs with additional dielectric caps are formed on the FET source/drain regions such that the dielectric sidewall spacer is between the gate and the metal plugs and between the dielectric cap and the additional dielectric caps. The dielectric cap, dielectric sidewall spacer and additional dielectric caps are different materials preselected to be selectively etchable, allowing for misalignment of a contact opening to the gate without risking exposure of any metal plugs and vice versa.

公开(公告)号：US10062617B2

公开(公告)日：2018-08-28

申请号：US15373852

申请日：2016-12-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Murat Kerem Akarvardar ,  Andreas Knorr

IPC: H01L21/70 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/762 ,  H01L21/308 ,  H01L29/78 ,  H01L29/16 ,  H01L29/161

CPC classification number: H01L21/823821 ,  H01L21/3083 ,  H01L21/3105 ,  H01L21/32105 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/7842 ,  H01L29/7849

Abstract: A method of forming SRB finFET fins first with a cut mask that is perpendicular to the subsequent fin direction and then with a cut mask that is parallel to the fin direction and the resulting device are provided. Embodiments include forming a SiGe SRB on a substrate; forming a Si layer over the SRB; forming an NFET channel and a SiGe PFET channel in the Si layer; forming cuts through the NFET and PFET channels, respectively, and the SRB down to the substrate, the cuts formed on opposite ends of the substrate and perpendicular to the NFET and PFET channels; forming fins in the SRB and the NFET and PFET channels, the fins formed perpendicular to the cuts; forming a cut between the NFET and PFET channels, the cut formed parallel to the fins; filling the cut with oxide; and recessing the oxide down to the SRB.