公开(公告)号：US10424553B2

公开(公告)日：2019-09-24

申请号：US15339693

申请日：2016-10-31

Applicant: Micron Technology, Inc.

Inventor： Suresh Yeruva ,  Kyle K. Kirby ,  Owen R. Fay ,  Sameer S. Vadhavkar

IPC: H01L23/00 ,  H01L23/24 ,  H01L21/56 ,  H01L23/31

Abstract: Semiconductor devices with underfill control features, and associated systems and methods. A representative system includes a substrate having a substrate surface and a cavity in the substrate surface, and a semiconductor device having a device surface facing toward the substrate surface. The semiconductor device further includes at least one circuit element electrically coupled to a conductive structure. The conductive structure is electrically connected to the substrate, and the semiconductor device further has a non-conductive material positioned adjacent the conductive structure and aligned with the cavity of the substrate. An underfill material is positioned between the substrate and the semiconductor device. In other embodiments, in addition to or in lieu of the con-conductive material, a first conductive structure is connected within the cavity, and a second conductive structure connected outside the cavity. The first conductive structure extends away from the device surface a greater distance than does the second conductive structure.

公开(公告)号：US09917002B2

公开(公告)日：2018-03-13

申请号：US15369089

申请日：2016-12-05

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Kunal R. Parekh

IPC: H01L21/74 ,  H01L21/768 ,  H01L21/265 ,  H01L29/66

CPC classification number: H01L21/743 ,  H01L21/26513 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76898 ,  H01L21/823475 ,  H01L23/481 ,  H01L23/49816 ,  H01L27/0694 ,  H01L27/10888 ,  H01L27/10894 ,  H01L29/66568 ,  H01L29/78 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548

Abstract: Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. Method of fabricating the semiconductor device can include etching a via into a semiconductor substrate, filling the via with a metal material, forming a metal routing layer subsequent to filling the via, and removing a portion of a bottom of the semiconductor substrate to expose a bottom region of the metal filled via.

公开(公告)号：US20170213760A1

公开(公告)日：2017-07-27

申请号：US15369089

申请日：2016-12-05

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Kunal R. Parekh

IPC: H01L21/74 ,  H01L21/265 ,  H01L29/66 ,  H01L21/768

CPC classification number: H01L21/743 ,  H01L21/26513 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76898 ,  H01L21/823475 ,  H01L23/481 ,  H01L23/49816 ,  H01L27/0694 ,  H01L27/10888 ,  H01L27/10894 ,  H01L29/66568 ,  H01L29/78 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548

Abstract: Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. Method of fabricating the semiconductor device can include etching a via into a semiconductor substrate, filling the via with a metal material, forming a metal routing layer subsequent to filling the via, and removing a portion of a bottom of the semiconductor substrate to expose a bottom region of the metal filled via.

公开(公告)号：US20170207139A1

公开(公告)日：2017-07-20

申请号：US15478133

申请日：2017-04-03

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Kyle K. Kirby ,  Luke G. England ,  Jaspreet S. Gandhi

IPC: H01L21/66 ,  H01L23/00

CPC classification number: H01L22/32 ,  H01L22/14 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02163 ,  H01L2224/0391 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/13005 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/00014 ,  H01L2924/1461 ,  H01L2924/00012 ,  H01L2924/206 ,  H01L2924/01047 ,  H01L2924/00 ,  H01L2224/05552

Abstract: An interconnect assembly includes a bond pad and an interconnect structure configured to electrically couple an electronic structure to the bond pad. The interconnect structure physically contacts areas of the bond pad that are located outside of a probe contact area that may have been damaged during testing. Insulating material covers the probe contact area and defines openings spaced apart from the probe contact area. The interconnect structure extends through the openings to contact the bond pad.

公开(公告)号：US09627295B2

公开(公告)日：2017-04-18

申请号：US15059020

申请日：2016-03-02

Applicant: Micron Technology, Inc.

Inventor： Anurag Jindal ,  Jian He ,  Lalapet Rangan Vasudevan ,  Kyle K. Kirby ,  Hongqi Li

IPC: H01L23/48 ,  H01L21/76 ,  H01L23/52 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L23/481 ,  H01L21/76801 ,  H01L21/76838 ,  H01L21/76898 ,  H01L23/522 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of manufacturing semiconductor devices and semiconductor devices with through-substrate vias (TSVs). One embodiment of a method of manufacturing a semiconductor device includes forming an opening through a dielectric structure and at least a portion of a semiconductor substrate, and forming a dielectric liner material having a first portion lining the opening and a second portion on an outer surface of the dielectric structure laterally outside of the opening. The method further includes removing the conductive material such that the second portion of the dielectric liner material is exposed, and forming a damascene conductive line in the second portion of the dielectric liner material that is electrically coupled to the TSV.

公开(公告)号：US09607930B2

公开(公告)日：2017-03-28

申请号：US15144065

申请日：2016-05-02

Applicant: Micron Technology, Inc.

Inventor： Jeffery W. Janzen ,  Michael Chaine ,  Kyle K. Kirby ,  William M. Hiatt

IPC: H01L23/48 ,  H01L25/065 ,  H01L21/768 ,  H01L23/525 ,  H01L23/60 ,  H01L25/00 ,  H01L21/50 ,  H01L23/52 ,  H01L21/82 ,  H01L23/62 ,  H01L23/00 ,  H01L27/02

CPC classification number: H01L23/481 ,  H01L21/50 ,  H01L21/76898 ,  H01L21/82 ,  H01L23/52 ,  H01L23/525 ,  H01L23/60 ,  H01L23/62 ,  H01L24/17 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0248 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17051 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/13034 ,  H01L2924/00014

Abstract: Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a backside, an interconnect extending through the first die to the backside, an integrated circuit electrically coupled to the interconnect, and a first electrostatic discharge (ESD) device electrically isolated from the interconnect. A second microelectronic die has a front side coupled to the backside of the first die, a metal contact at the front side electrically coupled to the interconnect, and a second ESD device electrically coupled to the metal contact. In another embodiment, the first die further includes a substrate carrying the integrated circuit and the first ESD device, and the interconnect is positioned in the substrate to disable an electrical connection between the first ESD device and the interconnect.

公开(公告)号：US20170040375A1

公开(公告)日：2017-02-09

申请号：US15299103

申请日：2016-10-20

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Steve Oliver

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L21/76898 ,  H01L27/14612 ,  H01L27/14625 ,  H01L27/14632 ,  H01L27/14643

Abstract: Semiconductor devices may include a semiconductor substrate comprising at least one of transistors and capacitors may be located at an active surface of the semiconductor substrate. An imperforate dielectric material may be located on the active surface, the imperforate dielectric material covering the at least one of transistors and the capacitors. Electrically conductive material in contact openings may be electrically connected to the at least one of transistors and capacitors and extend to a back side surface of the semiconductor substrate. Laterally extending conductive elements may extend over the back side surface of the semiconductor substrate and may be electrically connected to the conductive material in the contact openings. At least one laterally extending conductive element may be electrically connected to a first transistor or capacitor and may extend laterally underneath a second, different transistor or capacitor to which the laterally extending conductive element is not electrically connected.

Abstract translation: 半导体器件可以包括包括晶体管中的至少一个的半导体衬底，并且电容器可以位于半导体衬底的有源表面。 无孔介电材料可以位于有源表面上，无孔介电材料覆盖晶体管和电容器中的至少一个。 接触开口中的导电材料可以电连接到晶体管和电容器中的至少一个并且延伸到半导体衬底的背侧表面。 横向延伸的导电元件可以在半导体衬底的背侧表面上延伸并且可以与接触开口中的导电材料电连接。 至少一个横向延伸的导电元件可以电连接到第一晶体管或电容器，并且可以在横向延伸的导电元件未电连接的第二不同的晶体管或电容器的下方横向延伸。

公开(公告)号：US20160233160A1

公开(公告)日：2016-08-11

申请号：US15133121

申请日：2016-04-19

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Kunal R. Parekh ,  Philip J. Ireland ,  Sarah A. Niroumand

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/02063 ,  H01L21/76843 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53271 ,  H01L2224/13025 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599

Abstract: Microelectronic devices with through-silicon vias and associated methods of manufacturing such devices. One embodiment of a method for forming tungsten through-silicon vias comprising forming an opening having a sidewall such that the opening extends through at least a portion of a substrate on which microelectronic structures have been formed. The method can further include lining the sidewall with a dielectric material, depositing tungsten on the dielectric material such that a cavity extends through at least a portion of the tungsten, and filling the cavity with a polysilicon material.

Abstract translation: 具有通硅通孔的微电子器件及其相关制造方法。 一种用于形成钨硅通孔的方法的一个实施例，包括形成具有侧壁的开口，使得所述开口延伸穿过已经形成有微电子结构的衬底的至少一部分。 该方法可以进一步包括用介电材料衬里侧壁，在介电材料上沉积钨，使得空腔延伸穿过钨的至少一部分，并用多晶硅材料填充空腔。

公开(公告)号：US09099457B2

公开(公告)日：2015-08-04

申请号：US13850840

申请日：2013-03-26

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Kunal R. Parekh

IPC: H01L29/40 ,  H01L23/498 ,  H01L21/74 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/48 ,  H01L27/108 ,  H01L29/78 ,  H01L27/06

CPC classification number: H01L21/743 ,  H01L21/26513 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76898 ,  H01L21/823475 ,  H01L23/481 ,  H01L23/49816 ,  H01L27/0694 ,  H01L27/10888 ,  H01L27/10894 ,  H01L29/66568 ,  H01L29/78 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548

Abstract: Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. Method of fabricating the semiconductor device can include etching a via into a semiconductor substrate, filling the via with a metal material, forming a metal routing layer subsequent to filling the via, and removing a portion of a bottom of the semiconductor substrate to expose a bottom region of the metal filled via.

Abstract translation: 描述了具有垂直延伸穿过器件的一部分到半导体衬底背面的金属互连的半导体器件。 金属互连的顶部区域垂直位于包含金属布线层的水平平面的下方。 制造半导体器件的方法可以包括将通孔蚀刻到半导体衬底中，用金属材料填充通孔，在填充通孔之后形成金属布线层，以及去除半导体衬底的底部的一部分以露出底部 金属填充通孔的区域。

公开(公告)号：US08859425B2

公开(公告)日：2014-10-14

申请号：US13652033

申请日：2012-10-15

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Kunal R. Parekh

IPC: H01L21/768

CPC classification number: H01L23/49827 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49811 ,  H01L24/05 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2924/014

Abstract: Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming one or more openings in a front side of the semiconductor device and forming sacrificial plugs in the openings that partially fill the openings. The method further includes further filling the partially filled openings with a conductive material, where individual sacrificial plugs are generally between the conductive material and a substrate of the semiconductor device. The sacrificial plugs are exposed at a backside of the semiconductor device. Contact regions can be formed at the backside by removing the sacrificial plugs.

Abstract translation: 本文公开了制造半导体器件的方法。 根据特定实施例配置的方法包括在半导体器件的前侧形成一个或多个开口，并且在部分填充开口的开口中形成牺牲塞。 该方法还包括用导电材料进一步填充部分填充的开口，其中各个牺牲插塞通常在导电材料和半导体器件的衬底之间。 牺牲插头暴露在半导体器件的背面。 可以通过去除牺牲塞在背面形成接触区域。