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    ELECTRONIC CIRCUIT
    162.
    发明申请
    ELECTRONIC CIRCUIT 有权
    电子电路

    公开(公告)号：US20110222255A1

    公开(公告)日：2011-09-15

    申请号：US13040915

    申请日：2011-03-04

    Applicant: Naofumi KITANO ,  Toshiro NISHIMURA

    Inventor： Naofumi KITANO ,  Toshiro NISHIMURA

    IPC: H05K7/02

    CPC classification number: H05K1/0231 ,  H01L23/49827 ,  H01L23/50 ,  H01L2224/16225 ,  H05K1/0251 ,  H05K1/113 ,  H05K1/165 ,  H05K3/4614 ,  H05K2201/09236 ,  H05K2201/09636 ,  H05K2201/10545 ,  H05K2201/10636 ,  H05K2201/10674 ,  Y02P70/611

    Abstract: An electronic circuit is obtained that has reduced EMI levels. The circuit includes an integrated circuit, which is a source of noise, a bypass capacitor, and a circuit substrate on which they are mounted. An electronic circuit one electrode terminal of the bypass capacitor and one connecting electrode of the integrated circuit are connected through a first wire interconnect formed in the circuit substrate, and, additionally, another electrode terminal of the bypass capacitor and another connecting electrode of the integrated circuit are connected through a second wire interconnect, and the gap between the first wire interconnect and the second wire interconnect is made smaller than either the gap between the one connecting electrode and the other connecting electrode on the integrated circuit or the gap between the one electrode terminal and the other electrode terminal of the bypass capacitor.

    Abstract translation: 获得具有降低的EMI电平的电子电路。 电路包括作为噪声源的集成电路，旁路电容器和安装在其上的电路基板。 旁路电容器的一个电极端子和集成电路的一个连接电极的电子电路通过形成在电路基板中的第一线路互连而连接，另外，旁路电容器的另一个电极端子和集成电路的另一个连接电极 通过第二导线互连连接，并且使第一线互连和第二线互连之间的间隙小于集成电路上的一个连接电极和另一个连接电极之间的间隙或者一个电极端子之间的间隙 旁路电容器的另一个电极端子。

    MULTI-LAYER SUBSTRATE
    164.
    发明申请
    MULTI-LAYER SUBSTRATE 有权
    多层基板

    公开(公告)号：US20100282503A1

    公开(公告)日：2010-11-11

    申请号：US12675678

    申请日：2007-08-31

    Applicant: Taras Kushta

    Inventor： Taras Kushta

    IPC: H05K1/11

    CPC classification number: H05K1/0251 ,  H05K1/0219 ,  H05K1/0222 ,  H05K1/0245 ,  H05K1/116 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/09454 ,  H05K2201/09618 ,  H05K2201/09636 ,  H05K2201/09718 ,  H05K2201/09781

    Abstract: A multi-layer substrate includes a planar transmission line structure and a signal via, which are connected by a multi-tier transition. The multi-tier transition includes a signal via pad configured to serve for a full-value connection of the signal via and the planar transmission line; and a dummy pad connected to the signal via, formed in an area of a clearance hole in a conductor layer disposed between a signal terminal of the signal via and the planar transmission line, and isolated from the conductor layer.

    Abstract translation: 多层基板包括通过多层转换连接的平面传输线结构和信号通孔。 多层转换包括经配置以用于信号通孔和平面传输线的全值连接的信号通孔; 以及连接到信号通孔的虚拟焊盘，形成在设置在信号通孔的信号端子和平面传输线之间并与导体层隔离的导体层中的间隙孔的区域中。

    Shielded via
    165.
    发明授权
    Shielded via 有权
    屏蔽通过

    公开(公告)号：US07781889B2

    公开(公告)日：2010-08-24

    申请号：US11477703

    申请日：2006-06-29

    Applicant: Bram Leader ,  Richard R. Doersch

    Inventor： Bram Leader ,  Richard R. Doersch

    IPC: H01L23/48 ,  H01L23/535 ,  H05K3/42

    CPC classification number: H05K1/0222 ,  H01L2924/0002 ,  H05K1/115 ,  H05K3/429 ,  H05K2201/09636 ,  H05K2201/09809 ,  H01L2924/00

    Abstract: A system may include a first conductive ground pad, a second conductive ground pad, a first conductive via coupling the first ground pad to the second ground pad, a first conductive signal trace, a second conductive signal trace, and a second conductive via disposed within the first conductive via and coupling the first conductive signal trace to the second conductive signal trace. The first conductive ground pad and the second conductive ground pad may be disposed between the first conductive signal trace and the second conductive signal trace.

    Abstract translation: 系统可以包括第一导电接地焊盘，第二导电接地焊盘，将第一接地焊盘耦合到第二接地焊盘的第一导电通孔，第一导电信号迹线，第二导电信号迹线和设置在第二接地焊盘内的第二导电通孔 第一导电通孔并将第一导电信号迹线耦合到第二导电信号迹线。 第一导电接地焊盘和第二导电接地焊盘可以设置在第一导电信号迹线和第二导电信号迹线之间。

    Design method and system for minimizing blind via current loops
    166.
    发明授权
    Design method and system for minimizing blind via current loops 有权
    通过电流回路最小化设计方法和系统

    公开(公告)号：US07765504B2

    公开(公告)日：2010-07-27

    申请号：US11829179

    申请日：2007-07-27

    Applicant: Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Roger D. Weekly

    Inventor： Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Roger D. Weekly

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  H05K1/0216 ,  H05K1/115 ,  H05K3/0005 ,  H05K2201/09636

    Abstract: A design method and system for minimizing blind via current loops provides for improvement of electrical interconnect structure design without requiring extensive electromagnetic analysis. Other vias in the vicinity of a blind via carrying a critical signal are checked for suitability to conduct return current corresponding to the critical signal that is disrupted by the transition from a layer between two metal planes to another layer. The distance to the return current via(s) is checked and the design is adjusted to reduce the distance if the distance is greater than a specified threshold. If the blind via transition is to an external layer, suitable vias connect the reference plane at the internal end of the blind via to an external terminal. If the transition is between internal layers, suitable vias are vias that connect the two reference planes surrounding the reference plane traversed by the blind via.

    Abstract translation: 用于最小化盲通过电流回路的设计方法和系统提供了电互连结构设计的改进，而不需要广泛的电磁分析。 检查通过携带关键信号的盲目附近的其他通孔是否​​适合于进行对应于由两个金属平面之间的层到另一层之间的过渡而被破坏的关键信号的返回电流。 检查通过（s）的返回电流的距离，并且如果距离大于指定的阈值，则设计被调整以减小距离。 如果盲目通过转换到外部层，合适的通孔将盲通孔内部的参考平面连接到外部端子。 如果过渡在内层之间，合适的通孔是连接围绕由盲孔通过的参考平面的两个参考平面的通孔。

    Semiconductor package substrate
    168.
    发明授权
    Semiconductor package substrate 有权
    半导体封装基板

    公开(公告)号：US07732913B2

    公开(公告)日：2010-06-08

    申请号：US11701767

    申请日：2007-02-02

    Applicant: Tsung-Tien Hsieh ,  Wen-Jung Chiang ,  Yu-Po Wang ,  Cheng-Hsu Hsiao ,  Sen-Yen Yang

    Inventor： Tsung-Tien Hsieh ,  Wen-Jung Chiang ,  Yu-Po Wang ,  Cheng-Hsu Hsiao ,  Sen-Yen Yang

    IPC: H01L23/04

    CPC classification number: H01L23/49827 ,  H01L23/64 ,  H01L2223/6638 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0245 ,  H05K1/0251 ,  H05K1/114 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/09636 ,  H05K2201/09718 ,  H01L2924/00

    Abstract: A semiconductor package substrate is provided, which includes a substrate body having a plurality of conductive through holes formed therein, wherein at least two adjacent conductive through holes are formed as a differential pair, each of which has a ball pad formed at an end thereof; and at least one electrically integrated layer formed in the substrate body, and having an opening corresponding to the two adjacent conductive through holes formed as the differential pair and the ball pads thereof. Thus, the spacing between the conductive through holes and the electrically integrated layer and the spacing between the ball pads can be enlarged by the opening, so as to balance the impedance match.

    Abstract translation: 提供了一种半导体封装基板，其包括其中形成有多个导电通孔的基板主体，其中至少两个相邻的导电通孔形成为差分对，每个导体通孔在其一端形成有球垫; 以及形成在所述基板主体中的至少一个电气集成层，并且具有与形成为所述差动对的两个相邻的导电通孔对应的开口及其球垫。 因此，可以通过开口来扩大导电通孔和电气集成层之间的间隔以及球垫之间的间隔，从而平衡阻抗匹配。

    Integrated circuit package for high-speed signals
    169.
    发明授权
    Integrated circuit package for high-speed signals 有权
    用于高速信号的集成电路封装

    公开(公告)号：US07671450B2

    公开(公告)日：2010-03-02

    申请号：US12060387

    申请日：2008-04-01

    Applicant: Ellis E. Nease ,  Ashley Rebelo ,  Christopher J. Wittensoldner

    Inventor： Ellis E. Nease ,  Ashley Rebelo ,  Christopher J. Wittensoldner

    IPC: H01L23/50

    CPC classification number: H05K1/0251 ,  H01L23/49827 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2223/6638 ,  H01L2924/0002 ,  H01L2924/19051 ,  H01L2924/3011 ,  H05K1/0245 ,  H05K1/115 ,  H05K2201/09236 ,  H05K2201/09627 ,  H05K2201/09636 ,  H05K2201/09727 ,  H01L2924/00

    Abstract: An integrated circuit package having a multi-segment transmission line transformer for impedance matching a packaged integrated circuit, such as a driver or receiver, to a printed circuit board (PCB) transmission line to which the packaged chip is attached by, for example, solder balls. In one exemplary embodiment, a three-segment transmission line transformer provides improved broadband performance with the advantage of having a middle segment with a flexible length for easier routing. The length of each end segment of the three-segment transformer is adjusted to provide at least partial cancellation of reflections between the PCB and the transformer, and between the transformer and a circuit on the integrated circuit, respectively. Further, the inductive reactance of the solder balls and via wiring may be cancelled out by the transformed chip impedance to provide a non-inductive termination to the PCB transmission line at approximately one-half the highest data rate of the channel.

    Abstract translation: 一种具有多段传输线变压器的集成电路封装，用于将封装集成电路（例如驱动器或接收器）与包装芯片通过例如焊料连接到的印刷电路板（PCB）传输线进行阻抗匹配 球。 在一个示例性实施例中，三段式传输线变压器提供了改进的宽带性能，其优点在于具有具有灵活长度的中间段以便于路由。 三段式变压器的每个端段的长度被调整以分别提供PCB和变压器之间以及变压器与集成电路上的电路之间的反射的至少部分消除。 此外，焊球和通孔布线的感抗可能被转换的芯片阻抗抵消，以便以通道的最高数据速率的大约一半提供对PCB传输线的非感性端接。

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